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General Description
1.5.5
Interrupts
The 990/10A uses 16 priority-vectored interrupt levels. The priority ranking system assigns numbers
to the levels from 0 (highest priority) to 15 (lowest priority) in order to resolve interrupt conflicts. The
interrupts are also maskable via bits 12-15 of the status register. Upon detection of a pending inter-
rupt, the processor compares the interrupt code with the interrupt mask. If the level of the interrupt
is less than or equal to the mask level (higher or equal priority), the processor recognizes the inter-
rupt and initiates a context switch after completion of the currently executing instruction. The pro-
cessor fetches the new context workspace pointer and program counter from the appropriate inter-
rupt
vector
location
and
stores
the
previous
workspace
pointer,
program
counter,
and
status
register contents in workspace registers 13 through 15 of the new workspace. The processor then
loads the interrupt mask with a value that is one less than the value of the interrupt being processed
(except for a level 0 interrupt which loads 0 into the mask). This allows only interrupts of a higher
priority to interrupt the service routine. The processor also inhibits additional
interrupts until the
first instruction of the service routine has been processed. All interrupts are tested during prefetch
of the next instruction. Interrupts are sampled beginning at the first state of the prefetch cycle until
one state prior to the end of the destination write cycle.
In addition to the interrupts already discussed, there are two interrupts that are not affected by the
interrupt mask. One is referred to as the NMI. This is a level -1 interrupt that vectors through loca-
tions > FFFC and > FFFE. This is normally used for front panel control. The other is an illegal opera-
tion code interrupt that is normally a level 2 interrupt; but, on the 990/10A, it cannot be masked out
'via the status register. This allows software emulation of instructions not defined on the 990/10A
microprocessor.
1.5.5.1
Level 0 Interrupt (Power
Restored).
The highest
priority level is reserved
for the power
restored interrupt. When power is restored, TILINE power reset (TLPRES-) from the power supply re-
mains
true
long
enough
for the power
supply
to stabilize,
and
then
goes
false. TLPRES-
true
(RESET) forces the microprocessor to cease instruction execution. When TLPRES- goes false after
being true, the microprocessor initiates a level 0 interrupt trap (power restored). This level 0 interrupt
trap never completes on the 990/10A.
When
the microprocessor recognizes RESET (TLPRES-
true), it sends the RESET
bus status code
until the level 0 trap is initiated. The single instruction execute controller in the CRU chip recognizes
this RESET bus status code and forces an NMI. The result is that the level 0 interrupt context switch
completes (first instruction fetched), but this first instruction is not executed because an NMI is pre-
sent and the NMI
interrupt trap is initiated.
The NMI handler in ROM (see paragraph 1.5.5.8) then runs self-test because the NMI occurred due to
power restored (or power-up).
Following
a successful
completion
of self-test, under the right cir-
cumstances, a level 0 interrupt context switch then occurs. See the power-up NMI paragraph in this
section for a detailed explanation of what happens on power-up.
1.5.5.2
Level 1 Interrupt (Power Failure Imminent).
When the chassis power supply senses a loss
of power, a level 1 interrupt is generated. The hardware has several milliseconds of processing time
from the time the interrupt signal is asserted until
a master clear (TLPRES-) is issued.
2302633-9701
1-11
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