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1.5.2.2
Map Initialization.
General Description
On
power-up,
bit 8 of the status
register is set to zero. Mapping
is
disabled so that the first 31K words of memory are addressed. This memory may or may not be on-
board the 990/10A depending
upon the setting of the lower-bound address switches.
NOTE
A 990/10A operating in the auxiliary mode will only service certain in-
terrupts as specified in paragraph A.2.2. If these interrupts are to be
handled out of local memory, the map chip must be set up to map all
interrupts into the on-board address
space as determined
by the
memory bound switches. See Appendix A for additional information
on auxiliary mode operation.
NOTE
The
"greater
than'
symbol
(>)
is used
to represent
hexadecimal
numbers.
1.5.2.3
TILINE Peripheral Control Space (TPCS) Mapping.
The TPCS consists of those logical ad-
dresses in the range of > F800 through > FBFE, and is reserved for assignment to peripheral device
controllers. These addresses are modified before presentation to the TILINE. Five address bits are
appended
to the left (MSB) side of each
address
to form a 20-bit TILINE
word
address.
In other
words, addresses > F800 through > FBFE
are mapped to addresses > FFCO0O through > FFDFE. This
particular mapping occurs only when
map file zero is invoked (Status register bit 8 equals 0) or if
mapping is disabled. Figure 1-2 illustrates the TPCS concept.
2302633-9701
NOTE
Note from Table 1-2 that DRAM
addressed
in the 128-kilobyte incre-
ment from > FQO000 to > FFFFF overlaps the TPCS. The 990/10A in-
cludes logic to prevent accessing both memory and control registers
when
its
lower-bound
memory
address
switches
and
amount
of
memory jumpers permit addressing memory
in this range. However,
TILINE expansion memory should be limited so that memory does
not respond to TPCS
addresses. (In other words, lower-bound
ad-
dress switches on TILINE memory
controllers should not be set so
that
> FFCOO through > FFFFF are valid addresses.)
1-7
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