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General Description
1.5.5.3
Level 2 Interrupt (Error Conditions).
A level 2 interrupt can be caused by error conditions
external to the microprocessor as well as by internal microprocessor chip errors. The external error
conditions
are
memory
data
error,
memory
map
error,
and
TILINE
time-out.
The
internal
microprocessor chip level 2 interrupts include arithmetic overflow interrupt and the privileged op-
code interrupt as well as the macroinstruction decode trap.
The macroinstruction decode signal is used to indicate an illegal opcode in the 990/10A. Upon detec-
tion of an undefined opcode, the microprocessor chip traps (Subroutine call) using the workspace
pointer (WP) and program counter (PC) stored in locations > 0008 and > OOOA. These locations con-
tain the level 2 interrupt vectors.
The
990/10A
implementation
differs
from
the
990/10
with
regard
to
level
2 interrupts.
The
macroinstruction decode trap is not maskable with the interrupt mask logic and therefore overrides
any other interrupt. Also, the trap does not change the interrupt mask.
A flag indicating which condition caused the level 2-interrupt is stored in the error status register.
Error Status Register.
The error status register stores error conditions and provides a composite
output to the level 2 interrupt of the microprocessor. The error status register is read through the
CRU at CRU base address > 1FCO. Table 1-3 gives the bit definitions for the error status register.
Table 1-3.
Error Status Register CRU Bit Definitions
CRU
BASE
IFCO (HEX)
ERROR
CONDITION
INPUT
BIT
OUTPUT
BIT
TILINE
TIMEOUT
15
15
PRIVILEGE
VIOLATION
14
14
ILLEGAL
OPERATION
CODE
13
13
MEMORY
ERROR
12
12
MAPPING
ERROR
11
11
ARITHMETIC
OVERFLOW
4
4
RESERVED
3
RESERVED
2
ID
(990/10A
= 1)
l
ID
(990/10-990/12
INDICATOR)
0
BIT1
BITO
0
0
990/10
1
0
990/10A
0
1
990/12
1-12
2302633-9701
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