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2-1-8.
Terminal Voltage of CCD Imager
The terminal voltage of the CCD imager is given in Table
2-1.
In order to input a signal that has the specified timing and
voltage
for
these
terminals,
the
timing
IC
(IC916,
CXD1253R)
for
generation
of vertical
and
horizontal
transfer clocks
and
PG
clock and -V driver IC (IC918,
CXD1250N) are necessary. The block diagram is shown in
Fig. 2-13.
Pin No. | Symbol
Pin Description
Vertical register transfer clock
Vertical register transfer clock
|os
| ve | Vertical register transfer clock
10
OUT
Signal output
VDD
| Output amplifier drain bias
aa [eno]
SUB
PCB (overflow drain) voltage
1
H1
Horizontal register transfer clock
H2
Horizontal register transfer clock
20
|_20 | TP2 [inputbias
|
Waveform
Voltage
,
Input bias
DC
15V
eae cena ee a ee
Rake
Vertical register transfer clock
sro
reser
-9V, OV, 15V
[8 | Ves | Output ampier source
DC elf bias) _
Output amplifier gate bias
pc
Approx. 10V
U fe}
1
12
VL
Protection transistor bias
oc
Adjustment value,
13
Pre-charge gate clock
ek 5
mae ee
adjustment value +5V
|
Do
:
XV1
to XV4 are the vertical transfer clock. In order to
obtain a 3-value pulse, XSG1 and XSG2 are overiapped on
XV1 and XV3. XSUB is the throwaway pulse for electronic
shutter operations. H1 and H2 are the horizontal transfer
clock, and PG is the pre-charged gate clock.
The pin assignment and the timing chart for the timing IC
are shown in Fig.2-14 and Fig. 2-15.
-9V, OV
-9V, OV, 15V
GND
pc
Adjustment value
{Adjustment value,
adjustment value +24V)*
OV, 5V
( )* In the electronic shutter mode
Table 2-1.
"CCD Terminal Voigtage
27
#
3160
Fig. 2-13.
CCD Drive Circuit Block Chart
28
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