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4-3-7.
Noise Canceler Circuit
{1) Principles of noise cancel
—
ea, eT
c
Fig. 4-27.
Noise cancel
Since the playback Y signal (PB Y) noise component is
almost
completely
in the
high-frequency
range,
the
high-range component is extracted with an HPF. Noise can
be thought of as a cluster of smail-amplitude signals. It is
present particularly in the high-frequency range of the Y
signal. There
is a high-range component
also in the Y
signal itself, whose amplitude is considerably larger than
Limiting
Y signal high-range component
i?)
Noise component
~— Y signal high-range component
\
he
that of the noise
component.
Therefore,
the extracted: :
high-range component is limited, the Y signal high-range
component is subtracted from the resulting signal and the
noise
component
is extracted.
This
prevents
Y signal
high-range
component
dropouts.
After this, the
noise! ©
component is removed from the original Y signal.
IC101
CXA1207AR
V REG
Fig. 4-28.
Noise cancel circuit
The
playback
Y signal
is input to Pin
@
of IC101
(CXA1207AR), The high-range component of this signal is
extracted by the high-pass filter consisting of capacitor and
resistor and then fed to Pin
© and Pin @. The Pin @ input
is fed to the subtraction circuit via the LIM circuit, and then
subtracted from the Pin @ input to compensate the Y signal
high-range component for noise component extraction.
After that it passes through the LPF, its level is set at the. :
attenuator circuit and it is 'subtracted from the original
Y
signal to generate the Y signal with its noise component!
~
subtracted.
Although the noise cancellation amount is set by the serial : :
control
signal, the characteristics
is determined
by the:
=
capacitor and the resister of Pin @ and Pin @.
"4-3-8. Character insertion Circuit and VD Insertion
* Circuit
Insert the date in EE mode, with the analog SW !C141
(NJM2235M).
ql
1C144
NJM2235M
"eNt0s
1C104
cG REC BRANK
CKAIZOTAR
CG REC DATA
SYNC
or
|
Fig. 4-29.
VD and HD insertion circuit
.
When playback, if Pin @ of IC101 (CXA1207AR) is set to
-"H" at the timing of VD and HD, the potential is changed
into sink chip one in the DDS circuit at this period,
_Accordingly
VD
and
HD
are inserted
into regenerative
signals.
101014
CXA1207AR
Fig. 4-30. VD and HD Insertion circuit
Character insertion circuit (1)
In CXA1207AR the character signal is inserted to the DDS
circuit inside the IC by applying the OS DISP BLANK pulse
into Pin @ and the OS DISP DATA pulse into Pin @ in the
- ON SCREEN mode. (Fig. 4-31)
ICt04
CXA1207AR
viobt
OS DISP DATA
OS
DISP
BLANK
Fig. 4-31.
Character insertion circuit
4-3-9,
Output Circuit
-
(Y¥ + C:ADJUST MODE)
|PBY CAMERA Y
Bat
CAMERA REC
PB
1C4104
CXAIZ07AaR
Fig. 4-32.
Video output circuit
This circuit sends the EE output or the playback signal to
the monitor TV.
The video output circuit consists of an operational amplifier,
AC feedback loop is applied externally for gain control.
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