Advertisement
(3) PS circuit
The phase of the carrier for frequency conversion is shifted
90° by every 1H only when the CH-B video head is in use
(when RF SW puise is "L").
This operation invert only the phase of the CH-B field of the
low-range conversion chroma signal shifted 90 ° by every
1H. Through this signal processing, phase of the crosstalk
component
in the playback chroma
signal is inverted in
relation to the original signal every 2H, which allows the
comb filter to remove it. This method of signal processing is
called PS (Phase Shift) system.
732kH2
chroma signa!
RF Sw
'c124
CXA1208R
Sl? MHz
5.17 MHz
C.F.
Carrier for freq. conv.
fsc + (47-1/8 ) fH
Fig. 4-42.
PS circuit
4-21
{4) APC circuit
During recording, the APC
circuit produces a 4.43 MHz
signal phase-locked
to the burst signal in the chroma.
signal.
The chroma signal output from the ACC amplifier and the
signal from the 4.43 MHz VXO (Variable X'tal Oscillator)
are input to the APC detection circuit. These two signals
are detected in the APC detection circuit only during burst
periods by the burst flag signal, and the APC error voltage
is obtained by integrating the detected wave by the APC"
LPF externally connected to Pin @ of IC121 (CXA1208R).
By feeding back this APC error voltage to the 4.43 MHz:
VXO, the oscillation frequency output from the 4.43 MHz
VXO
is phase-locked to the color burst signal within the
chroma signal output by the ACC amplifier.
Recording chroma signal
Burst flag
os
Detector
4.43MHz
V.X.0
APC error voltage
APC LPF
ict2i
CXA1208R
Fig. 4-43.
APC circuit
<
<.(8) AFC circuit
"<During recording, the AFC circuit produces a (47-1/8) ¢ fH
" (approx. 732 KHz) signal which is phase-locked to the H.
SYNC signal of the input video signal.
The output of the 375 » fH VCO is converted to frequency
-of fx by the 1/375 frequency divider, then input to the AFC
detection circuit and the AFC ID detection circuit.
The AFC
error signal is obtained
by phase comparison
"-petween the 1/375 frequency divider output and either of
the above input reference H in the AFC detection circuit,
"then the 375 + fH VCO is phase-locked. The 375 « fy VCO
"qutput phase-locked to H. SYNC by this AFC loop is
"divided to 1/8, then input to the carrier converter.
The
AFC
ID circuit
does
not
operate
while
AFC
is
phase-locked. It only works when the phase is unlocked.
* AFC ID
detection
IC 424
CXAI2Z08R
ey
fsc£(47-1/8) fr
C- SYNC
[1/375 frequency divider]
This frequency divider divides 375 » fa VCO output in the
following manner to create an fx-interval signal. When used
for PAL
system,
this divider can
be set to 1/375
by
switching the voltage at Pin @ of 1C121 (CXA1208R). Also,
the VCO circuit can be set to 375+ fH VCO for the PAL
system, by switching the voltage at Pin @.
[ Pin®
HO]
oo.
| Mode
PAL
| NTSC
{AFC detection]
The
phase
of the rising edge
of the AFC
DET
input
reference H is compared to the 1/375 divider output. The
AFC
error
signal
is output.
according
to the
phase
difference to controi the 375+ fH VCO
through the LPF
connected externally to Pin @ of CXA1208R.
fse (47 ~1/8) fi
5.17 MHz
C.F
Fig. 4-44.
AFC circuit
[AFC ID detection]
4-22
[Half-H killer circuit}
The H. SYNC signal is used as a comparison signal for
signal processing such as AFC; AFC ID (for recording) and
APC ID (for playback), etc.
This H. SYNC signal is created from the composite SYNC
separated from the input video signal. As the composite
SYNC
signal
contains
a 1/2H
equalizing
pulse
in the
vertical sync signal section, this must be removed.
Advertisement
