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Direct memory access
The addresses for the page register are as follows:
Eight DMA channels are supported by the system. Two
Intel® 8237-5 DMA controller chips (four channels in each
chip) are used. DMA channels are assigned as follows:
Page Register
/o Hex Address
DMA channel 0
0087
DMA channel 1
0083
CTLR 1
Ch
0
- -
Spare
Ch 1 - SDLC
Ch 2 -- Diskette
Ch 3- Spare
CTLR 2
DMA channel 2
0081
Ch 4- Cascade for CTRL 1
Ch 5- Spare
Ch 6- Spare
Ch 7- Spare
DMA channel 3
0082
DMA channel 5
008B
DMA channel 6
0089
DMA channel 7
008A
Refresh
008F
DMA channels
Channels 0 through 3 are contained in DMA controller
1.
Transfers
of
8-bit
data,
8-bit 1/O
adapters
and 8-bit
or
16-bit
system
memory
are
supported by
these channels.
Each
of
these channels
will
transfer
data in 64KB
blocks
throughout the 16-megabyte system address space.
Channels
4
through
7
are
contained
in DMA controller
2. To
cascade channels
0
through
3 to the
microproces-
sor, use
channel 4. Transfers
of
16-bit data
between
16-bit
adapters and 16-bit system memory are supported by
channels 5, 6 and 7. DMA channels 5 through 7 will
transfer data in
128KB blocks throughout the
16-
megabyte system address space. These channels will not
transfer data on odd-byte boundaries.
Address generation for the DMA channels is as follows:
For
DMA channels 3 through 0
Source DMA Page Registers 8237A 5
Address
A234
A16
A15A0
NOTE: To
generate
the
addressing signal "byte high
enable" (BHE), invert address line AO.
For DMA channels 7 through 5
Source DMA Page Registers8237A 5
Address
A234
A17
A16A1
NOTE:
The
BHE and
AO
addressing
signals
are
forced to
a logic 0. DMA channel addresses do not increase or
decrease
through
page
boundaries
(64KB
for
channels
0
through 3 and 128KB for channels 5 through 7).
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