Alert Pin - Texas Instruments 2 Series Manual

BQ76905
SLUSE97 – NOVEMBER 2023
a protection alert or fault has occurred, but will rely on the host to disable FETs. Using the device in standalone
mode requires that all settings are programmed into the OTP by TI. This is only available for cases involving a
significant shipment volume. Please contact your TI sales representative for information on this option.
The BQ76905 can also be entirely configured by a host processor writing all settings to the device's internal
registers across the serial communications interface, without requiring any OTP programming. Using this
approach, settings must be reloaded from the host each time the device is reset or enters SHUTDOWN mode
and is restarted.
7.4.8 ALERT Pin Operation
The BQ76905 includes functionality to generate an alarm signal at the ALERT pin, which can be used as
an interrupt to a host processor. The ALERT pin is an open-drain pin which will be pulled low by the device
whenever an alarm signal is generated. The alarm function includes a programmable mask, to allow the
customer to decide which flags or events can trigger an alarm. The selected alarm flags remain latched until the
host processor reads their status and clears the triggered alarm bits. The alarm mask can be changed during
field operation, to mask or unmask individual flags from generating an alarm signal. The device also provides
the unlatched, instantaneous value of each flag, in addition to the latched version. See the
Reference Manual for more details on this function.
7.4.9 Low Frequency Oscillator
The low frequency oscillator (LFO) in the BQ76905 operates continuously while in NORMAL and SLEEP modes,
and depending on setting is shutdown (except when needed) during DEEPSLEEP mode. The LFO runs at
approximately 262.144 kHz during NORMAL mode, and reduces to approximately 32.768 kHz in SLEEP mode.
The LFO is trimmed during manufacturing to meet the specified accuracy across temperature.
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7.4.10 I C Serial Communications Interface
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The I C serial communications interface in the BQ76905 device acts as a target device and supports rates
up to 400 kHz with an optional CRC check. The BQ76905 will initially power up by default in a mode
determined by the OTP settings factory programmed by TI. The host can change the CRC mode setting while in
CONFIG_UPDATE mode, then the new setting will take effect upon exit of CONFIG_UPDATE mode.
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The I C device address (as an 8-bit value including target address and R/W bit) is set by default as 0x10 (write),
0x11 (read), which can also be changed by the configuration setting.
The communications interface includes programmable timeout capability, with the internal I2C bus logic reset
when an enabled timeout occurs. This is described in detail in the
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An I C write transaction is shown in
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the Stop. The I C logic will auto-increment the register address after each data byte. The shaded regions show
when the device may be clock stretching.
SCL
A7 A6
SDA
Start
The CRC check is enabled by setting a data memory bit. When enabled, the CRC is calculated as follows:
• Note that the CRC is reset after each data byte and after each stop.
• In a single-byte write transaction, the CRC is calculated over the target address, register address, and data.
• In a block write transaction, the CRC for the first data byte is calculated over the target address, register
address, and data. The CRC for subsequent data bytes is calculated over the data byte only.
The CRC polynomial is x
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Figure 7-2. Block writes are allowed by sending additional data bytes before
...
A1 R7 R6
R/W ACK
Register
Target
Address
Address
Figure 7-2. I
8 2
+ x + x + 1, and the initial value is 0.
Product Folder Links:
BQ76905 Technical Reference
... ...
R0 D7 D6 D0
ACK ACK
Data
2
C Write
BQ76905
BQ76905 Technical
Manual.
...
C7 C6 C0
ACK
CRC
Stop
(optional)
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