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BQ76905
SLUSE97 – NOVEMBER 2023
7.4.2 Coulomb Counter and Digital Filters
The BQ76905 device monitors pack current using a low-side sense resistor that connects to the SRP and SRN
pins through an external RC filter, which should be connected such that a charging current will create a positive
voltage on SRP relative to SRN. The differential voltage between SRP and SRN is digitized by an integrated
delta-sigma coulomb counter ADC, which can digitize voltages over a ±200-mV range and uses multiple digital
filters to provide optimized measurement of the instantaneous, averaged, and integrated current. The device
supports a wide range of sense resistor values, with a larger value providing better resolution for the digitized
result. The maximum value of the sense resistor should be limited to ensure the differential voltage remains
within the ±200-mV range for system operation when the current measurement is desired. For example, a
system with a maximum discharge current of 200 A during normal operation (not a fault condition) should limit
the sense resistor to 1 mΩ or below.
Multiple digitized current values as well as an accumulated charge integration are available for readout over
the serial communications interface, including two using separate hardware digital filters, CC1 and CC2.
Further detail on the current measurements and charge integration results available are provided in
Measurement and Charge
7.4.3 Protection FET Drivers
The BQ76905 integrates low-side CHG and DSG FET drivers, which can directly drive low-side protection
NFET transistors. The device supports both series and parallel FET configurations, providing FET body diode
protection when configured for a series FET configuration, if one FET driver is on, and the other FET driver is
off. When body diode protection is enabled, the DSG driver may be turned on to prevent FET damage if the
battery pack is charging while a discharge inhibit fault condition is present. Similarly, the CHG driver may be
turned on if the pack is discharging while a charge inhibit fault condition is present. These decisions depend on
the detection of a current with an absolute value in excess of the programmable body diode threshold, which
uses the coulomb counter current measurement for its decision.
The DSG pin is driven high when not blocked by command and when no related faults (such as UV, OTD, UTD,
OCD1, OCD2, SCD, and select diagnostics) that are configured for autonomous control are present, or for body
diode protection. The driver can be forced on by command, but the command only takes effect if configuration
settings allow.
The DSG driver is designed to allow users to select an optimal resistance in series between the DSG pin and the
DSG FET gate to achieve the desired FET rise and fall time per the application requirement and the choice of
FET characteristics. When the DSG FET is turned off, the DSG pin drives low, and all overcurrent in discharge
protections (OCD1, OCD2, SCD) are disabled to better conserve power. These resume operation when the
DSG FET is turned on. Device configuration settings determine which protection autonomously controls the
appropriate FET driver.
The CHG pin is driven high only when not blocked by command and when no related faults (OV, OTC, UTC,
OCC, SCD, and select diagnostics) which are configured for autonomous control are present, or for body diode
protection. The driver can be forced on by command, but the command only takes effect if configuration settings
allow. Turning off the CHG pin has no influence on the overcurrent protection circuitry. The CHG FET driver
actively drives the CHG pin high when enabled, and actively drives the pin low to approximately 0.5 V above
the VSS voltage for about 100 μs when disabled, then allows the pin to settle to the PACK– voltage through the
external CHG FET gate-source resistor. If a charger is attached to the pack while the CHG FET is disabled, the
CHG pin can fall to a voltage as low as 25 V below the device VSS, per the device electrical specifications. Due
to the 100 μs time interval during which CHG is actively pulled low, the time constant of the CHG drive circuit
(made up of the driver effective resistance, any series resistance between the CHG pin and the CHG FET gate,
and the FET gate capacitance) should be kept well below this level.
The BQ76905 includes PWM drive capability on the CHG and DSG FET drivers, which allows them to limit the
average current flowing in a charge or discharge mode. The DSG FET driver actively drives the DSG pin high
or low, based on the driver control, so can implement continual switching to turn on and off the DSG FET. If a
charger is not attached, then the CHG driver can also implement continual switching in PWM mode. If a charger
is attached with voltage significantly above the pack voltage, then the CHG FET gate voltage is generally driven
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