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IC BLOCK DIAGRAM AND DESCRIPTION
SM5819AF(6-channel DSD-PCM converter)
DSIFL
DSIFR
DSICT
FIR FILTER
DSISL
and
DSISR
DOWN
DSISW
SAMPLING
UNIT
DSGAIN
SEL1FS
SEL4FS
ROM
24bit 720 word
(fs 240w)
(2fs 240w)
(3fs 240w)
XMTPCM
EXIFLT
EXISLR
EXIMCK
EXILRCK
EXIBCK
EXIMCK
SYNC
CLOCK
INIT
GENERATOR
and
DIRDSCK
TIMING
DSBCK
CONTROL
MCK
TEST1
TEST2
TEST3
No.
Name
I/O Description
1
VDDL
-
Core power supply
2
SEL1FS
I
PCM output rate select 1
3
SEL4FS
I
PCM output rate select 2
4
SELEXT
I
fs/2fs/4fs output and external data output select
5
DSGAIN
I
OSD signal gain setting
6
XMTPCM
I
PCM output mute control input
7
VDDH
-
I/O power supply
8
TEST1
I
Test input 1
9
TEST2
I
Test input 2
10
TEST3
I
Test input 3
11
TOUT1
O Test output 1
12
VSS
-
Ground
13
VDDL
-
Core power supply
14
DIRPCK
I
PCM output PBCK/PLRCK I/O select
15
FMTPCM
I
PCM output format select
16
VSS
-
Ground
17
MCKOUT
O System clock output
18
VDDH
-
I/O power supply
19
PBCK
I/O PCM output BCK bit clock
20
PLRCK
I/O PCM output LRCK word clock input
21
POSLR
O PCM data output:surround right/left channel
22
POCSW
O PCM data output:center/subwoofer channel
23
POFLR
O PCM data output:front right/left channel
24
VSS
O Ground
PCM
PCM
I/F
MUTE
INT/EXT.
DATA
SELECT
INT/EXT.
DATA
SELECT
(Internal Clocks)
TEST
CONTROL
VDDL
37
DSBCK
38
FMTPCM
DSIFL
39
DSIFR
40
DSICT
41
POFLR
DSISW
42
43
DSISL
POSLR
44
DSISR
POCSW
45
DIRDSCK
46
SYNC
SELEXT
47
INIT
48
VSS
PLRCK
PBCK
MCKOUT
DIRPCK
TOUT1
TOUT2
No.
Name
I/O Description
25
VDDL
-
Core power supply
26
TOUT2
-
Test output 2
27
MCKOUT
O Master clock input:512fs(22.5792MHz, fs=44.1kHz)
28
VSS
I
Ground
29
EXIMCK
-
External system clock input
30
VDDH
-
I/O power supply
31
EXIBCK
I
External PCM data BCK bit clock input
32
EXILRCK
I
External PCM data LRCK word clock input
33
EXISLR
I
External PCM data input:surround left/right channel
34
EXICSW
I
External PCM data input:center/subwoofer channel
35
EXIFLR
I
External PCM data input:front left/right channel
36
VSS
-
Ground
37
VDDL
-
Core power supply
38
DSBCK
I/O DSD data input bit clock. Controlled by DIRDSCK.
39
DSIFL
I
DSD data input:front left-channel
40
DSIFR
I
DSD data input:front right-channel
41
DSICT
I
DSD data input:center-channel
42
DSISW
I
DSD data input:front subwoofer-channel
43
DSISL
I
DSD data input:surround left-channel
44
DSISR
I
DSD data input:surround right-channel
45
DIRDSCK
I
DSBCK I/O select
46
SYNC
I
Forced synchronization input.
47
INIT
I
Initialization input. Active-LOW. Resync on "L"
48
VSS
-
Ground
TX-NR1000
24
VSS
23
POFUR
22
POCSW
21
POSLR
20
PLRCK
19
PBCK
18
VDDH
17
MCKOUT
16
VSS
15
FMTPCM
DIRPCK
14
13
VDDL
"H"
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