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IC BLOCK DIAGRAM AND DESCRIPTION
PCA9564PW(Parallel bus to I C-bus controller)
PIN CONFIGURATION Ð SO, TSSOP
V
1
20
D0
DD
2
19
D1
SDA
3
18
D2
SCL
4
17
D3
RESET
5
16
D4
INT
6
15
D5
A1
7
14
D6
A0
8
13
D7
CE
9
12
NC
RD
10
11
V
WR
SS
PCA9564
8
D0±D7
RD
WR
CE
A0
A1
RESET
V
DD
INT
2
PIN CONFIGURATION
PIN NUMBER
SYMBOL
SO, TSSOP
HVQFN
1, 2, 3, 4, 5,
1, 2, 3, 4,
D0±D7
6, 7, 8
5, 18, 19,
20
9
6
NC
10
7
V
SS
11
8
WR
12
9
RD
13
10
CE
14, 15
11, 12
A0, A1
16
13
INT
17
14
RESET
18
15
SCL
19
16
SDA
20
17
V
DD
BUS BUFFER
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
POWER-ON RESET
INTERRUPT CONTROL
TIMING
CLOCK
SELECTORS
INTERNAL
OSCILLATOR
Figure 1. Block diagram
PIN
PIN
NAME AND FUNCTION
TYPE
I/O
Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status
between the controller and the CPU. D0 is the least significant bit.
No connect: must be left floating
Pwr
Ground
I
Write Strobe: When LOW and CE is also LOW, the contents of the data bus is loaded into
the addressed register. The transfer occurs on the rising edge of the signal.
I
Read Strobe: When LOW and CE is also LOW, causes the contents of the addressed
register to be presented on the data bus. The read cycle begins on the falling edge of RD.
I
Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU and
the controller are enabled on D0±D7 as controlled by the WR, RD and A0±A1 inputs.
When HIGH, places the D0±D7 lines in the 3-State condition.
I
Address Inputs: Selects the controller internal registers and ports for read/write
operations.
O
Interrupt Request: Active-LOW, open-drain, output. This pin requires a pull-up device.
I
Reset: A LOW level clears internal registers resets the I
2
I/O
I
C-bus serial clock input/output (open-drain).
2
I/O
I
C-bus serial data input/output (open-drain).
Pwr
Power Supply: +2.3 to +3.6 V
INPUT
MASTER/SLAVE
FILTER
STATE MACHINES
TX-NR1000
2
C state machine.
SCL
SDA
V
SS
SD00707
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