Icom IC-701 Instruction Manual page 29

counter for the A and B VFOs, the digit selector to control
the up-down counters by a paralell data, A/B counter
selector, etc.
The CLOCK (CK) and UP/DOWN (UD) signals, which is
the output from the tuning knob/chopper circuit, are fed to
Pins 12 and 19 respectively. The clock signal is in
proportion to the rotation of the tuning knob, and the
up/down signal is dependant on the direction of rotation
of the tuning knob. When the UD signal is HIGH, the
up/down counter increases the frequency in proportion to
the number of CK pulses, and when the UD is LOW, the
frequency is decreased in the same way. The signal which
is determined by the "A" or "B'' position of the VFO
switch on the front panel, becomes the SL signal. This is
fed to Pin 14 and selects either "A" or "B'" set of
up/down counters.
If you push the Tuning Speed button on the front panel,
the signal is locked in the driver unit and fed to Pin 17 as
the Y signal. In this case the Kilohertz and Hundred Hertz
digits are cleared to 0, the CK signal is fed to the 10KHz
digit counter, which results in high speed tuning.
The FCL KO-K8 pins of IC1 are connected to the ACC
socket on the rear panel through the driver unit. When a
high level signal is supplied to FCL Pin 11 and KO-K2 at the
same time, the 10MHz digit figure can be reset, according
to the input data at KO-K2. Then when the high level signal
is supplied from KO-K8, any figure can be set according to
the data from the higher digit to the lower.
For use with an EXT controller, resetting of the frequency
can be accomplished in the same manner through the ACC
socket.
When the Band Select switch is at the 7-28MHz position,
no signal to these pins is required; however, at the 1.8MHz
or 3.5MHz position, since a figure of 8 or 5 is necessary on
the 100KHz digit for the bottom of each band, when
switching bands or turning the power ON, a signal is
supplied to these terminals. Therefore, when the Band
Select switch on the front panel is at the 1.8MHz or 3.5MHz
position, the high level signal is supplied to K8 to set 8 on
the 100KHz digit or K4 and K1 to set 5 on the 100KHz
digit respectively at the bottom of each band after the
FCL input.
By the input of CK and UD signals, or by resetting the
up/down counter, the output signals appear at AOQ-B4 and
are supplied to the driver unit. The output signals of
A2-A4 are supplied to the PLL programmable divider for
determination of the divider ratio in accordance with the
up/down.
6-3-4 LOOP FILTER CIRCUIT
The phase-detected signal from Pin 40 of IC1 is fed to the
loop filter circuit of 1C3. This circuit changes the output
of the phase detector, which is a pulse, into a DC voltage,
and also decides the response time of the whole loop. The
output is used as the voltage to control the VCO frequency.
6-3-5 VCO CIRCUIT
Q11-016 of the VCO unit are FET modified Clapp
oscillators, used separately for each band. Q11 is for the
1.8MHz band and Q16 is for the 28MHz band. To obtain
the desired frequency, the D/A converter tracks the
variation of the voltage supplied to the tuning diodes D11,
D14, D17, D20, D23 or D26. Also, the output signal from
the loop filter is supplied to the tuning diodes D12, D175,
D18, D21, D24, or D27 to lock the VCO frequency.
The oscillation frequency of the VCO is equal to the
displayed frequency plus about 9MHz. This output is
supplied from P1 to the mixer circuit of the RF unit after
the buffer amplifier Q1 and Q2. Also, the VCO output is
supplied to the PLL mixer through the buffer amplifier of
Q4. Q5-010 and D4-D9 are to switch the DC power source
to Q11-Q16 according to the operating band.
6-3-6 D/A (DIGITAL TO ANALOG) CONVERTER
CIRCUIT
The PLL unit has two D/A converters. R89-R94 are
connected to A2-B4 of IC1 and act as a D/A converter for
the higher digits. The output signal is amplified by half of
IC2 for VCO tracking.
The other D/A converter is for the VXO circuit. The signals
from AO-D1 of IC1 are buffered by IC4 and IC5 and
supplied to R101-R109 for D/A conversion. The converted
signal is fed to the other half of IC2 for off-set voltage
setting and amplification to control the frequency of the
VXO circuit. This D/A converted voltage changes in steps
to give 100Hz step variation to the VXO frequency. Q14
and Q15 are employed to maintain linearity of the D/A
converter output for changes in mode. R68 and R70 adjust
the correction factor.
6-3-7 POWER CIRCUIT
The power circuit of the PLL consists of Q12, Q13, and
IC9. Q13 is turned ON by C144 and applies voltage to
IC9. IC9 is a voltage regulator whose output is 8.2 Volts.
A part of this output is divided at R55 and R56 and is
added to the base of O12. The emitter of Q12 is connected
to the collector of Q13 through a Zener diode (6.1 Volt)
and therefore the collector voltage is held at 10.6 Volts. As
you can see, the output of the power circuit of the PLL has
outputs of 8.2 and 10.6 Volts regulated DC.
Q10 and Q11 are negative voltage regulators. One of Q11's
bases is grounded and the other is connected to R53 and
R54. R53 is connected to +8.2 Volts, and R54 to the
collector of Q10. —9 Volts is added to the emitter of Q10
and its base is connected to the collector of Q11. Q11
works as a differential amplifier, so if there is a difference
between the divided voltage at R53 and R54 and the
potential of the other base, which is ground, the difference
is amplified until the voltage of Q10's collector is the same
value as the positive output of IC9. Therefore, the output
of —8.2 Volts is achieved.
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