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obtained from the collector of 034.
When the AGC switch is in the SLOW position, the output
signal of Q28 is fed to another peak hold detector, O29.
The detected DC voltage charges C99 and switches Q30 ON
and
Q31
OFF.
When
the input signal is removed,
the
charged voltage of C99 is discharged through R159 and 031
is switched ON, and the charged voltage in C101 and C102
is discharged
through
R164
and Q31.
Thus the AGC
voltage is held during the time constant of C99 and R159.
When the AGC switch is in the FAST position, —9 Volts is
applied to the base of O30, turning it OFF, and turning
Q31 ON.
Therefore the AGC voltage does not hold, and
the AGC
release time is determined
by C101
and
R192.
The AGC attack time varies with the mode of operation, so
when
the mode
is changed, so are the determining fixed
resisitors.
C101 and C102 are the capacitors that are in the
circuit for all modes, and determine the time constant along
with the following resistors:
For USB and LSB, R166 and
R192
(in paralell), both of which are located on the "A"
unit. For CW and RTTY, R192 and R48, which are located
on the mode switch (in series); As the time constant circuit
may be charged during transmit, Q35 is designed to be ON
during transmit time, through D33, and shunts C101 and
C102. When the power is turned ON, a pulse through R173
and C103 turns ON Q35 temporarily to discharge C101 and
C102
in order to allow the AGC voltage to recover to a
non-signal bias state.
.
Q36 superimposes the RF Gain control voltage on the AGC
line by way of the emitter follower, forming a threshold-
type RF gain control.
As the RF AGC circuit operates as
the ALC circuit during transmit, Q36 is biased through D31
to remove interference troubles.
INPUT
SIGNAL
of
1C1
HIGH
MIC GAIN
LOW
Limiting
MIC GAIN
a
OUTPUT
SIGNAL
of
!C1
6-2
TRANSMITTER
6-2-1
MICROPHONE
AMPLIFIER
CIRCUIT
Voice signals from the microphone are passed through the
MIC Gain control on the front panel and applied to Q17,
the ALC
attenuator,
located
on
"A"
unit.
The
ALC
voltage is applied to the gate of Q17, which
changes the
source-to-drain impedance.
Accordingly, the ALC controls
the voice signal passing through 017. The signal is then fed
to amplifiers Q15 and Q16 and then sent to the balanced
modulator.
6-2-2
BALANCED
MODULATOR
CIRCUIT
IC5 is a balanced
modulator
where
the BFO signal, fed
through
Pin
10, and the voice signal, fed through
Pin 4,
result in a double side band signal output from Pins 6 and
12.
When
the mode switch is in the CW, CW-N
or RTTY
mode, power for the MIC AMP circuit is turned OFF and
therefore, the voice signal is not applied to IC5.
Instead,
a voltage from
D23 is applied to Pin 4, IC5 loses balance,
and the BFO signal becomes the output.
This signal is used
for the carrier in CW and RTTY operation.
During RTTY
operation, the frequency is shifted according to the keying
in the BFO.
During CW operation, a key is connected to
the base of 014.
The key turns Q14 ON and OFF at the
keying
rate, therefore, turning OFF
D22 and the carrier,
ON and OFF at the keying rate.
When
the speech processor circuit is not used, the output
signal of 1C5 (DSB signal) is fed to the crystal filter FL1
through
D21, D22 and D34.
FL1 cuts the unwanted side
band of the DSB
signal and the output is a Single Side
Band signal.
(CW and RTTY signals pass through FL1 as
unchanged wave forms).
From the filter, the signal is sent
to the RF unit through P1.
OUTPUT
SIGNAL
of
FL1
LOW
COMP
LEVEL
(Low Drive Level)
Limiting
Level
HIGH COMP
LEVEL
(High Drive Level)
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Ae he
LOW
COMP
LEVEL
(Low Drive Level)
HIGH COMP
LEVEL
(High Drive Level)
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