ASIX AX88796ALF Manual

3-in-1 local bus fast ethernet controller
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10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller
Features
Highly integrated with embedded 10/100Mbps
MAC, PHY and Transceiver
Embedded 8K * 16 bit SRAM
Compliant
100BASE-TX specification
NE2000 register level compatible instruction
Single chip local CPU bus 10/100Mbps Fast
Ethernet MAC Controller
Support both 8 bit and 16 bit local CPU
interfaces include MCS-51 series, 80186 series,
MC68K series CPU and ISA bus
Support both 10Mbps and 100Mbps data rate
Support
both
operation
Provides an extra MII port for supporting other
media. For example, Home LAN application
Product description
The AX88796A Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller
with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88796A supports both 8 bit and 16 bit local
CPU interfaces include MCS-51 series, 80186 series, and MC68K series CPU and ISA bus. The AX88796A implements
both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88796A also
provides an extra IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using
MII interface, Home LAN PHY type media can be supported.
As well as, the chip also provides optional Standard Print Port (parallel port interface), can be used for printer server device
or treat as simple general I/O port.
System Block Diagram
51 series
/
186 bus
series
/
68K bus
series
/
ISA bus
ASIX ELECTRONICS CORPORATION
4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsin-Chu City, Taiwan, R.O.C. 300
TEL: 886-3-579-9500
3-in-1 Local Bus Fast Ethernet Controller
with Embedded SRAM
with
IEEE
802.3/802.3u
full-duplex
or
half-duplex
8bit / 16bit
non-PCI bus
AX88796A
10/100 Mbps
PHY/TxRx
FAX: 886-3-579-9558
Document No.: AX88796A/V1.12/01/09/13
Support EEPROM interface to store MAC
address
External and internal loop-back capability
Support Standard Print Port for printer server
application
Support up to 3/1 General Purpose In/Out pins
128-pin LQFP low profile package
0.25 Micron low power CMOS process. 25MHz
Operation, Pure 3.3V operation with 5V I/O
tolerance.
RoHS compliant package
*IEEE is a registered trademark of the Institute of
Electrical and Electronic Engineers, Inc.
*All other trademarks and registered trademark are
the property of their respective holders.
Optional
Home LAN
PHY
With
1
AX88796ALF
Optional Print Port
Or General I/O Ports
RJ11
RJ45
Release Date: 01/09/2013
http://www.asix.com.tw

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Summary of Contents for ASIX AX88796ALF

  • Page 1 186 bus AX88796A series With 10/100 Mbps 68K bus PHY/TxRx series RJ45 ISA bus ASIX ELECTRONICS CORPORATION Release Date: 01/09/2013 4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsin-Chu City, Taiwan, R.O.C. 300 TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw...
  • Page 2 Designers must not rely on the absence or characteristics of any features or registers marked “reserved”, “undefined” or “NC”. ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before starting a design of ASIX products.
  • Page 3: Table Of Contents

    5.1.8 Receive Status Register (RSR) Offset 0CH (Read) ...................39 5.1.9 Inter-frame gap (IFG) Offset 16H (Read/Write) ....................40 5.1.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write) ...............40 5.1.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write) ...............40 Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 4 APPENDIX A: APPLICATION NOTE........................63 A.1 U 25MH ............................63 SING RYSTAL A.2 U 25MH ...........................63 SING SCILLATOR APPENDIX B: POWER CONSUMPTION REFERENCE DATA ................64 APPENDIX C: NOTICE OF AX88796A ........................65 REVISION HISTORY ..............................67 Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 5 APPING TAB - 17 PHY R ........................43 MBEDDED EGISTERS TAB - 18 MII M ......................49 ANAGEMENT RAME ORMAT TAB - 19 MII M ..................49 ANAGEMENT RAMES FIELD ESCRIPTION Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 6: Introduction

    EECK SEEPROM EEDI Core EEDO Remote & PHY+ MII I/F NE2000 FIFOs Tranceiver / GPIO Registers Print Port General Host Interface Ctl BUS SA[9:0] SD[15:0] Fig - 1 AX88796A Block Diagram Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 7: Pin Connection Diagram

    VDDA TXD[3] Local CPU Bus VSSA GPI[2]/SPD 10/100BASE MAC I_OP EECS Controller IO_BASE[0] EECK IO_BASE[1] EEDI IO_BASE[2] EEDO GPO[0] TEST2 /IOCS16 CLKO25M SD[0] SD[1] SD[2] Fig - 2 Pin Connection Diagram Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 8: Pin Connection Diagram With Spp Port Option

    10/100BASE MAC I_OP EECS Controller IO_BASE[0] EECK IO_BASE[1] EEDI IO_BASE[2] EEDO GPO[0] TEST2 (With SPP Port) /IOCS16 CLKO25M SD[0] SD[1] SD[2] Fig - 3 Pin Connection Diagram with SPP Port Option Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 9: Pin Connection Diagram For Isa Bus Mode

    10/100BASE MAC I_OP EECS Controller IO_BASE[0] EECK IO_BASE[1] EEDI IO_BASE[2] EEDO GPO[0] TEST2 (for ISA Bus I/F) /IOCS16 CLKO25M SD[0] SD[1] SD[2] Fig - 4 Pin Connection Diagram for ISA Bus Mode Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 10: Pin Connection Diagram For 80X86 Mode

    GPI[2]/SPD 10/100BASE MAC I_OP EECS Controller IO_BASE[0] EECK IO_BASE[1] EEDI IO_BASE[2] EEDO GPO[0] TEST2 (for x86 Bus I/F) CLKO25M SD[0] SD[1] SD[2] Fig - 5 Pin Connection Diagram for 80x86 Mode Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 11: Pin Connection Diagram For Mc68K Mode

    GPI[2]/SPD 10/100BASE MAC I_OP EECS Controller IO_BASE[0] EECK IO_BASE[1] EEDI IO_BASE[2] EEDO GPO[0] TEST2 (for 68K Bus I/F) CLKO25M SD[0] SD[1] SD[2] Fig - 6 Pin Connection Diagram for MC68K Mode Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 12: Pin Connection Diagram For Mcs-51 Mode

    GPI[2]/SPD 10/100BASE MAC I_OP EECS Controller IO_BASE[0] EECK IO_BASE[1] EEDI IO_BASE[2] EEDO GPO[0] TEST2 (for 8051 Bus I/F) CLKO25M SD[0] SD[1] SD[2] Fig - 7 Pin Connection Diagram for MCS-51 Mode Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 13: Signal Description

    PSEN: This signal is active low for 8051 program access. For I/O device, AX88796A, this signal is active high to access the chip. This signal is for 8051 bus application only. TAB - 1 Local CPU bus interface signals group Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 14: 10/100Mbps Twisted-Pair Interface Pins Group

    When in link status and line activity occurrence, the output will be blinking. (Current sink capacity is 8mA) TAB - 3 Built-in PHY LED indicator pins group Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 15: Eeprom Signals Group

    PHYs. The transfer protocol has to meet the IEEE 802.3u MII specification. For more information, please refer to section 6.5 CPU Access MII Station Management functions. TAB - 5 MII interface signals group Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 16: Standard Printer Port (Spp) Interface Pins Group (Optional)

    When SPP port is selected. The pin is defined as SLCT. Default “1”. The pin reflects write register offset 17h bit 0 inverted GPO[0] value. TAB - 7 General Purposes I/O pins group Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 17: Miscellaneous Pins Group

    Power Supply: +3.3V DC. 53, 104, 114, 126 28, 34, Power Supply: +0V DC or Ground Power. 43, 52, 54, 63, 105,115,127 VDDA 56, 69, Power Supply for Analog Circuit: +3.3V DC. 73, 82 Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 18: Gpio/Mii Configuration Setup Signals Cross Reference Table

    Description /SPP_SET Standard Printer Port Selection: /SPP_SET = 0: Standard Printer Port or GPIO is selected /SPP_SET = 1: MII port is selected (default) TAB - 9 GPIO/MII Configuration Setup Table Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 19: Memory And I/O Mapping

    The word_2 to word_4 will map to PROM of 6 bytes Ethernet address. Start bit OP code Address Data A7 ~ A0 D15 ~ D0 (Ref. EEPROM datasheet) AX88796A auto load timing format Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 20: I/O Mapping

    BAH (E’NET ADDRESS 5) 98H (E’NET ADDRESS 4) 0402H 76H (E’NET ADDRESS 3) 54H (E’NET ADDRESS 2) 0400H 32H (E’NET ADDRESS 1) 10H (E’NET ADDRESS 0) TAB - 14 PROM Map 0400H ~ 040FH Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 21: Basic Operation

    DA38 DA37 DA36 DA35 DA34 DA33 DA32 PAR5 DA47 DA46 DA45 DA44 DA43 DA42 DA41 DA40 Note: The bit sequence of the received packet is DA0, DA1, … DA7, DA8 …. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 22: Multicast Address Match Filter

    The first bit of received packet sequence is 1’s stands by Multicast Address. Note: Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 23: Broadcast Address Match Filter

    Aggregate Address not Match The meaning of AB, AM and PRO signals, please refer to “Receive Configuration Register” Aggregate Address Filter function will be: Logic /Bro /Mul Logic Logic /Bro Logic Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 24: Buffer Management Operation

    … Page Start Buffer #1 Buffer #2 Buffer #3 … … … … Buffer #n Page Stop 8000h Physical Memory Map Logic Receive Buffer Ring Fig - 8 Receive Buffer Ring Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 25: Fig - 9 Receive Buffer Ring At Initialization

    Boundary Pointer Register. If the two values are equal the reception is aborted. The Boundary Pointer Register can be used to protect against overwriting any area in the receive buffer ring that has not yet been Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 26 Register. This is necessary to activate the AX88796A’s Remote DMA channel. 8. Remove one or more packets from the receive buffering. 9. Reset the overwrite warning (OVW, overflow) bit in the Interrupt Status Register. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 27 The received CRC is always stored in buffer memory after the last byte of received data for the packet. Error Recovery If the packet is rejected as shown, the DMA is restored by the AX88796A by reprogramming the DMA starting address pointed to by the Current Page Register. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 28: Packet Transmission

    2. At least one byte has entered the FIFO. (This indicates that the burst transfer has been started). 3. If a collision had been detected then before transmission the packet backoff time must have timed out. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 29 Source Address 5 Type / Length 0 Type / Length 1 Data 0 Data 1 … … WTS = 1 in Data Configuration Register. This format is used with MC68K Mode. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 30: Filling Packet To Transmit Buffer (Host Fill Data To Memory)

    Start Address. The DMA Address will be incremented and the Byte Counter will be decremented after each transfer. The DMA is terminated when the Remote Byte Count Register reaches a count of zero. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 31: Removing Packets From The Ring (Host Read Data From Memory)

    AX88796A. The advantage of this scheme is that it easily differentiates between buffer full and buffer empty: it is full if BNRY = CPR; empty when BNRY = CPR-1. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 32 Source Address 5 Type / Length 0 Type / Length 1 Data 0 Data 1 … … WTS = 1 in Data Configuration Register. This format is used with MC68K Mode. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 33 Source Address 5 Type / Length 0 Type / Length 1 Data 0 Data 1 … WTS = 0 in Data Configuration Register. This format is used with ISA, 80186 or MCS-51 Mode. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 34: Other Useful Operations

    7. Read data current receive buffer by Remote DMA read operation. 8. Compare the received data with original transmit data and check if it is equal. 9. Repeat step 5 to step 8 for more packets test. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 35: Registers Operation

    Inter-frame Gap (IFG) GPOC 18H – 1AH Standard Printer Port (SPP) Standard Printer Port (SPP) 1BH – 1EH Reserved Reserved Reset Reserved TAB - 15 Page 0 of MAC Core Registers Mapping Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 36: Tab

    Inter-frame Gap (IFG) GPOC 18H – 1AH Standard Printer Port (SPP) Standard Printer Port (SPP) 1BH – 1EH Reserved Reserved Reset Reserved TAB - 16 Page 1 of MAC Core Registers Mapping Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 37: Command Register (Cr) Offset 00H (Read/Write)

    Indicates that a packet was received with one or more of the following errors CRC error Frame Alignment Error FIFO Overrun Missed Packet Packet Transmitted Indicates packet transmitted with no error Packet Received Indicates packet received with no error. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 38: Interrupt Mask Register (Imr) Offset 0Fh (Write)

    These encoded configuration bits set the type of loop-back that is to be performed. LB1 LB0 Mode 0 Normal operation Mode 1 Internal AX88796A loop-back Mode 2 PHYcevisor loop-back Inhibit CRC 0: CRC appended by transmitter. 1: CRC inhibited by transmitter. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 39: Transmit Status Register (Tsr) Offset 04H (Read)

    Enable the receiver to accept and save packets with error. 5.1.8 Receive Status Register (RSR) Offset 0CH (Read) FIELD NAME DESCRIPTION Reserved Receiver Disabled Multicast Address Received. Missed Packet FIFO Overrun Frame alignment error. CRC error. Packet Received Intact Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 40: Inter-Frame Gap (Ifg) Offset 16H (Read/Write)

    Test pin Enable, default value is logic 0 (User always keep the default value unchanged) Select Test Pins Output, default value is logic 0 (User always keep the default value unchanged) Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 41: Test Register (Tr) Offset 15H (Read)

    MPSEL I_LINK GPI0 Media Selected Internal PHY Internal PHY External MII PHY Internal PHY Depend on MPSET bit Reserved /GPO0 Default “0”. The register reflects to GPO[0] pin with inverted value. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 42: Spp Data Port Register (Spp_Dpr) Offset 18H (Read/Write)

    /ATFD pin reflects the inverted value of this signal. STRB Setting a low-high-low pulse on this register is used to strobe the print data into the printer. /STRB pin reflects the inverted value of this signal. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 43: The Embedded Phy Registers

    0.7 (COLTST) Collision Test. When this bit is set to a 1, the PHY will assert the MCOL signal in response to MTX_EN. 0.6:0 (RESERVED) Reserved. All bits will read 0. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 44: Mr1 - Status Register Bit Descriptions

    Model Number. 6-bit model number of the device. The model number is programmable. Default value: 6’h02. 3.3:0 (VERSION[3:0]) Revision Number. The value of the present revision number. The version number is programmable. Default value: 4’h1. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 45: Mr4 - Autonegotiation Advertisement Registers Bit Descriptions

    These bits are similar to the bits defined for the MR4 register (see Table 16). 5.4:0 (LP_SELECT) Selector Field. This field contains the type of message sent by the link partner. For IEEE 802.3 compliant link partners, this field should read 00001. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 46: Mr5 -Autonegotiation Link Partner (Lp) Ability Register (Next Page) Bit Descriptions

    Page Received. When this bit is set to 1, it indicates that a NEXT_PAGE has been received. Link Partner Autonegotiation Capable. When this bit is set to 1, it (LP_NWAY_ABLE) indicates that the link partner is autonegotiation capable. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 47: Cpu I/O Read And Write Functions

    Even-Byte Odd-Byte Not Valid Word Access Odd-Byte Even-Byte 80186 CPU bus I/O Write function Function Mode /BHE /IORD /IOWR SD[15:8] SD[7:0] Standby Mode Byte Access Even-Byte Odd-Byte Word Access Odd-Byte Even-Byte Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 48: Mc68K Cpu Bus Type Access Functions

    Standby Mode High-Z High-Z High-Z High-Z Byte Access Not Valid Even-Byte Not Valid Odd-Byte 8051 bus I/O Write function Function Mode /PSEN /IORD /IOWR SD[15:8] SD[7:0] Standby Mode Byte Access Even-Byte Odd-Byte Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 49: Cpu Access Mii Station Management Functions

    Idle Condition. The IDLE condition on MDIO is a high-impedance state. All three state drivers will be disabled and the PHY’s pull-up resistor will pull the MDIO line to logic 1. TAB - 19 MII Management Frames- field Description Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 50: Electrical Specification And Timings

    7.3 DC Characteristics (Vdd=3.0V to 3.6V, Vss=0V, Ta=0C to 75C) Description Units Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage Vdd-0.4 Input Leakage Current Output Leakage Current Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 51: Timing Characteristics

    Typ. Units Tcyc CYCLE TIME Thigh CLK HIGH TIME Tlow CLK LOW TIME Tr/Tf CLK SLEW RATE 7.4.2 Reset Timing LCLK/XTALIN RESET Symbol Description Typ. Units Trst Reset pulse width LCLK Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 52: Isa Bus Access Timing

    OUTPUT ENABLE TIME FROM /IORD Tdis(RD) OUTPUT DISABLE TIME FROM /IORD T iord IORD LOW REQUIRE TIME LCLK T idle IORD HI REQUIRE TIME 1.5 (*) LCLK (*) Reference Notic of AX88796A item 3 Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 53 T iowr IOW WIDTH TIME LCLK T cycle CYCLE TIME FOR EVEREY DATA PORT WRITE LCLK T idle IOWR HI REQUIRE TIME 1.5 (*) LCLK (*) Reference Notic of AX88796A item 3 Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 54: 80186 Type I/O Access Timing

    OUTPUT ENABLE TIME FROM /IORD Tdis(RD) OUTPUT DISABLE TIME FROM /IORD Tiord IORD LOW WIDTH TIME LCLK Tidle IORD HI REQUIRE TIME 1.5 (*) LCLK (*) Reference Notic of AX88796A item 3 Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 55 DATA HOLD TIME Tiorw /IOWR WIDTH TIME LCLK Tcycle CYCYLE TIME FOR EVERY DATA PORT WRITE LCLK T idle IOWR HI REQUIRE TIME 1.5 (*) LCLK (*) Reference Notic of AX88796A item 3 Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 56: Type I/O Access Timing

    OUTPUT ENABLE TIME FROM /UDS OR /LDS Tdis(DS) OUTPUT DISABLE TIME FROM /UDS OR /LDS Tw(DS) /UDS OR /LDS WIDTH TIME LCLK Tidle IORD HI REQUIRE TIME 1.5 (*) LCLK (*) Reference Notic of AX88796A item 3 Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 57 DATA HOLD TIME Tw(DS) /UDS,/LDS LOW WIDTH LCLK Tcycle CYCYLE TIME FOR EVERY DATA PORT WRITE LCLK Tidle IOWR HI REQUIRE TIME 1.5 (*) LCLK (*) Reference Notic of AX88796A item 3 Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 58: 8051 Bus Access Timing

    OUTPUT DISABLE TIME FROM /IORD Tiord IORD LOW WIDTH TIME LCLK Tidle IORD HI REQUIRE TIME 1.5 (*) LCLK Tv (RDY) RDY VALID FROM IORD (*) Reference Notic of AX88796A item 3 Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 59 DATA SETUP TIME Th(WR) DATA HOLD TIME IOWR WIDTH LCLK iowr Tcycle I/O CYCLE WIDTH TIME LCLK Tidle IOWR HI REQUIRE TIME 1.5 (*) LCLK (*) Reference Notic of AX88796A item 3 Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 60: Mii Timing

    Data output hold time Trclk Cycle time(100Mbps) Trclk Cycle time(10Mbps) Trch high time(100Mbps) Trch high time(10Mbps) Trcl low time(100Mbps) Trcl low time(10Mbps) data setup time data hold time Trs1 RXER data setup time Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 61: Package Information

     SYMBOL MILIMETER MIN. 0.05 0.15 1.35 1.40 1.45 0.17 0.22 0.27 13.90 14.00 14.10 19.90 20.00 20.10 15.60 16.00 16.40 21.00 22.00 23.00 0.45 0.60 0.75 1.00  0° 7° Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 62: Ordering Information

    AX88796ALF 3-in-1 Local Bus Fast Ethernet Controller 9.0 Ordering Information Part Number Description 128 PIN, LQFP Package, Commercial grade 0C to +70 C AX88796ALF (Green, Lead-Free) Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 63: Appendix A: Application Note

    Note : The capacitors (33pF) may be various depend on the specification of crystal. While designing, please refer to the suggest circuit provided by crystal supplier. A.2 Using Oscillator 25MHz AX88796A CLKO 25M 25MHz XTALIN XTALOUT 3.3V Power OSC 25MHz Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 64: Appendix B: Power Consumption Reference Data

    The following reference data of power consumption are measured base on prime application, that is AX88796A + EEPROM, at 3.3V/25 °C room temperature. Item Test Conditions Typical Value Units Full traffic with 10Mbps, no LED drive Full traffic with 100Mbps, no LED drive No Link Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 65: Appendix C: Notice Of Ax88796A

    An external resistor needed. 20k ohm is placed from this signal to ground PIN 83 REXT100 REXT100 No external resistor An external resistor needed. 2.49k ohm is placed from this signal to ground Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 66 Write Data Port Page0 (0Dh) Read (0Dh) Reserved Page0 (0Eh) Read CRC error counter Page0 (0Fh) Read Miss Packet counter DP (10H) Read Data Port Reset (1Fh) Read (1Fh) Software reset Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 67: Revision History

    Changed the revision number in 3-digi format. Modified some document format. V1.11 2012/11/26 1. Corrected some typos in Section 1.3 and 2. V1.12 2013/01/09 1. Modified some descriptions in Section 3.1, Appendix C. Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
  • Page 68 AX88796ALF 3-in-1 Local Bus Fast Ethernet Controller 4F, No. 8, Hsin Ann Rd., HsinChu Science Park, HsinChu, Taiwan, R.O.C. TEL: 886-3-5799500 FAX: 886-3-5799558 support@asix.com.tw Email: Web: http://www.asix.com.tw Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.

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