ASIX AX88796ALF Manuals

Manuals and User Guides for ASIX AX88796ALF. We have 1 ASIX AX88796ALF manual available for free PDF download: Manual

ASIX AX88796ALF Manual (68 pages)

3-in-1 Local Bus Fast Ethernet Controller

Brand: ASIX | Category: Controller | Size: 1 MB

Table of Contents
3
Introduction
6
General Description
6
Ax88796A Block Diagram
6
Fig - 1 Ax88796A Block Diagram
6
Pin Connection Diagram
7
Pin Connection Diagram with SPP Port Option
8
Pin Connection Diagram for ISA Bus Mode
9
Pin Connection Diagram for 80X86 Mode
10
Fig - 5 Pin Connection Diagram for 80X86 Mode
10
Pin Connection Diagram for MC68K Mode
11
Pin Connection Diagram for MCS-51 Mode
12
Signal Description
13
Local Cpu Bus Interface Signals Group
13
10/100Mbps Twisted-Pair Interface Pins Group
14
Built-In PHY LED Indicator Pins Group
14
10/100Mbps Twisted-Pair Interfaces Pins Group
14
Eeprom Signals Group
15
MII Interface Signals Group (Optional)
15
Eeprom Bus Interface Signals Group
15
Standard Printer Port (SPP) Interface Pins Group (Optional)
16
General Purpose I/O Pins Group
16
Standard Printer Port Interface Pins Group
16
General Purposes I/Opins Group
16
Miscellaneous Pins Group
17
Gpio/MII Configuration Setup Signals Cross Reference Table
18
Miscellaneous Pins Group
18
Gpio/MII Configuration Setup Table
18
Memory and I/O Mapping
19
Eeprom Memory Mapping
19
Tab
19
Eeprom Data Format Example
19
Local Memory Mapping
19
I/O Mapping
20
Sram Memory Mapping
20
Tab
20
Tab - 13 Prom Map 00H ~ 1Fh
20
Tab - 14 Prom Map 0400H ~ 040Fh
20
Basic Operation
21
Receiver Filtering
21
Unicast Address Match Filter
21
Multicast Address Match Filter
22
Broadcast Address Match Filter
23
Aggregate Address Filter with Receive Configuration Setup
23
Buffer Management Operation
24
Packet Reception
24
Fig - 8 Receive Buffer Ring
24
Fig - 9 Receive Buffer Ring at Initialization
25
Packet Transmission
28
Filling Packet to Transmit Buffer (Host Fill Data to Memory)
30
Removing Packets from the Ring (Host Read Data from Memory)
31
Other Useful Operations
34
Registers Operation
35
Mac Core Registers
35
Tab
35
Of Mac Core Registers Mapping
35
Tab
36
Command Register (CR) Offset 00H (Read/Write)
37
Interrupt Status Register (ISR) Offset 07H (Read/Write)
37
Interrupt Mask Register (IMR) Offset 0FH (Write)
38
Data Configuration Register (DCR) Offset 0EH (Write)
38
Transmit Configuration Register (TCR) Offset 0DH (Write)
38
Transmit Status Register (TSR) Offset 04H (Read)
39
Receive Configuration (RCR) Offset 0CH (Write)
39
Receive Status Register (RSR) Offset 0CH (Read)
39
Inter-Frame Gap (IFG) Offset 16H (Read/Write)
40
Inter-Frame Gap Segment 1(IFGS1) Offset 12H (Read/Write)
40
Inter-Frame Gap Segment 2(IFGS2) Offset 13H (Read/Write)
40
MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)
40
Test Register (TR) Offset 15H (Write)
40
Test Register (TR) Offset 15H (Read)
41
General Purpose Input Register (GPI) Offset 17H (Read)
41
GPO and Control (GPOC) Offset 17H (Write)
41
SPP Data Port Register (SPP_DPR) Offset 18H (Read/Write)
42
SPP Status Port Register (SPP_SPR) Offset 19H (Read)
42
SPP Command Port Register (SPP_CPR) Offset 1AH (Read/Write)
42
The Embedded Phy Registers
43
MR0 - Control Register Bit Descriptions
43
Tab
43
MR1 - Status Register Bit Descriptions
44
MR2, MR3 - Identification Registers (1 and 2) Bit Descriptions
44
MR4 - Autonegotiation Advertisement Registers Bit Descriptions
45
MR5 - Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions
45
MR5 -Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions
46
MR6 - Autonegotiation Expansion Register Bit Descriptions
46
Cpu I/O Read and Write Functions
47
Isa Bus Type Access Functions
47
80186 Cpu Bus Type Access Functions
47
Mc68K Cpu Bus Type Access Functions
48
Mcs-51 Cpu Bus Type Access Functions
48
Cpu Access MII Station Management Functions
49
Tab - 18 MII Management Frame Format
49
TAB - 19 MII Management Frames- Field Description
49
Electrical Specification and Timings
50
Absolute Maximum Ratings
50
General Operation Conditions
50
DC Characteristics
50
Timing Characteristics
51
Xtal / Clock
51
Reset Timing
51
ISA Bus Access Timing
52
80186 Type I/O Access Timing
54
Type I/O Access Timing
56
8051 Bus Access Timing
58
MII Timing
60
Package Information
61
Ordering Information
62
Appendix A: Application Note
63
Using Crystal 25Mhz
63
Using Oscillator 25Mhz
63
Appendix B: Power Consumption Reference Data
64
Appendix C: Notice of Ax88796A
65
Revision History
67

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ASIX AX88796ALF Manual (68 pages)

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