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5.50
At the end of the main gate period the Qoutput of IC3a goes to logic '1' and
connects via pin 5 of the p.c.b. to the clock input of IC13b and the base of Q7
on the Control Assembly.
5. 51
C9 and R22 present a positive spike to the base of Q7 which switches on. The
negative-going spiked output of Q7 is the transfer pulse which is used to update
the display at the end of the main gate period.
5.52
Logic •Ji to the clock input of IC13b changes the
0
to logic
•o•.
One Ooutput
is taken to pin 3 of the p.c.b. whilst the other switches off Q5 allowing CJO to
charge via R26 and R23.
NOTE: The time taken to charge Cl 0 sets the display time.
5.53
Whilst CJO is charging, Q6 and Q8 are switched off, Q9 is on and QlO is off.
When the display time has expired i.e. Cl 0 charged, Q6 and Q8 switch on, Q9
switches off and QJO switches on. The negative reset pulse is taken from the collector of
QlO to clear IC13b and is also taken via pin 4 of the p.c.b. to clear IC3a on the Amplifier
and High Speed Decade Assembly. The positive reset pulse is taken from the collector of
Q9 and applied to the time base divider chain and the display assembly.
5.54
The
Q
output of logic
•o•
to pin 3 of the p.c.b. is taken to the J and K inputs of
IC3a on the Amplifier and High Speed Decade Assembly to ensure a main gate
period is not generated during the display time.
Sampling Rate
5.55
The sampling rate of the instrument depends upon two factors, the selected gate
time and the period for which the completed reading is displayed before the next
measurement is allowed to commence. The display time is governed by the time taken to
charge CJO and different values of R26 will, therefore, vary the sampling rate.
Wtanual Reset
5.56
By pressing the RESET button on the front panel, Q9 is switched off and the positive
and negative reset pulses are generated.
READOUT ASSEMBLY 11-0754 Fig.4.10
5.57
The instrument has a six digit in-line solid state latched display. The display
comprises hybrid micro-circuits consisting of a MSl decoder/driver circuit and an
array of
11
Ga
As P
11
light-emitting diodes. The decoder/driver provides 5 bits of latch
memory for the BCD and decimal point data, a BCD-to-4 x 7 decoder, and LED drivers.
5.58
IC3b, IC4a, IC5a, IC4b and IC5b of the Amplifier and High Speed Decade
Assembly are divide-by-two integrated circuits connected to form the first
decade divider.
5-8
9057/9059
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