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5.15
Two 100kHz outputs are taken from IC3, one output is taken to the main gate
control for period measurement whi 1st the other provides the signal input for the
self check facility.
Function/Selection (Refer to Fig.2.2on Page 5-5)
5.16
IC7 on the Control Assembly 19-0608 forms with IC1 and IC2 of the Amplifier
and High Speed Decade Assembly 19-0605 the electronic changeover switch for
frequency or period measurement selection.
5.17
With the lever switch on the front panel set to PERIOD, pin 33 of the p.c.b. is at
logic state '0' (taken to earth via the lever switch), therefore pin 1 of IC7a is at
logic '0', closing gate IC7a gate and inhibiting the 100Hz signal from IC6.
5.18
Pin 11 of IC7d is at logic '1', this is taken to IC1 b of the Amplifier and High
Speed Decade Assembly opening that gate and allowing the input signal which
has been amplified and shaped to pass to IC7c of the Control Assembly.
5.19
IC7c gate is open (pin 1 of IC7a at logic '0', therefore pin 10 of IC7c is at logic
'1') and the input signal is applied via IC1 c and IC7c to the Time Base Divider.
5.20
In the period measurement mode pins 12 and 13 of IC7d are at logic '0' resulting in
logic '1' at the output pin 11. This is taken to pin 1 of IC1a of the Amplifier and
High Speed Decade Assembly via pin 15 of the p.c.b. to open IC1a gate. IC2b gate is open
due to logic '1' on pin 9 (from IC2a) and logic '1' on pin 12 (no current flow through R45)
and the 100kHz from the Frequency Standard passes to the High Speed Decade via IC1a and
IC2b.
5.21
With the front panel switch in the FREQUENCY position, pin 33 of the p.c.b.
is at logic state '1' (no current flow through R17), therefore pin 1 of IC7a is at
logic '1' and IC7a gate is open. Pin 14 of the p.c.b. is also at logic '1' (piri 11 of IC7d
is at logic
'0';
therefore pin 12 of IC1c of Amplifier and High Speed Decade Assembly is at
logic '0' resulting in logic '1' output from IC1c to pin 14 of p.c.b. 19-0605) which opens
IC7c gate allowing the 100 Hz from the decade dividers to pass to the Time Base Divider.
5.22
As IC1b of the High Speed Decade Assembly is closed, the input signal path to the
Time Base Divider via pin 14 of the p.c.b. is inhibited. IC1a of the High Speed
Decade Assembly is also closed due to logic '0' on pin 1 via pin 15 of p.c.b. thus inhibiting
the 100kHz signal path to the High Speed Decade.
5.23
IC2a is open due to logic '1' on pins 1, 2 and 4. Logic '1' from pin 3 of IC1a
opens IC2b gate and the input signal passes through IC2a and IC2b to the High
Speed Decade.
Time Base Fig .4. 5
5.24
This consists of three Decade Counters IC9, IC10 and IC11 which divide either the
100 Hz output of the frequency standard to provide gate
·
times of 1 Oms, 1 OOms, 1s
5-3
9057/9059
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