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Automatic Cut-out
5.41
The Automatic Cut-out removes the load from the battery pack when the batteries
reach the discharged condition (below 4.5V) and illuminates fhe
'charge batteries' warning lamp on the front panel.
5.42
Q1 and Q2 form a cross coupled bistable circuit having their respective emitters
coupled to earth via the front panel lever switch.
5.43
When the instrument is switched on, the emitter of Q1 going to earth switches
Q1
1
or{ and places the +5V supply No.1 across RLA/2 operating the relay and
closing contacts RLA1 and RLA2 to provide a path for the power supplies to the p.c.b.'s and
the display assembly.
5.44
When the battery voltage falls below 4.5V, the voltage at the junction of R53 and
D3 will fall and the resulting drop in base voltage to Ql will cut Ql off. Relay
RLA/2 will drop out, opening RLAJ and RLA2 which removes the load from the power supply.
When QJ cuts off, the base voltage to Q2 increases the current through Q2 to light the
'charge batteries' lamp on the front panel. The lamp is connected between pin 19 and 23
of the p • c • b •
5.45
D2 at the collector of Q2 isolates the base of Ql from the 'charge batteries' lamp
supply.
Gating Control (Fig.4.5 and Fig.4.8)
5.46
Before a measurement can take place, the display, the time base divider chain
and control logic must be reset to their appropriate standby states. This is carried
out by the positive and negative-going RESET pulses. The negative pulse is generated at the
collector of QlO and taken to pin
1 of the amplifier and High Speed Decade Assembly p.c.b.
This negative pulse clears IC3a on the High Speed Decade Assembly and JCJ3b on the Control
Assembly setting their respective Q outputs to zero. The High Speed Decade bistables IC3,
IC4, IC5 and the overflow drive are also set to zero. The positive reset pulse appears at
the collector of Q9 and is taken to pin 4 of the p.c.b. where it connects to the Readout
Assembly and is used to set the counting decades in the display assembly to zero. The
positive reset pulse is also used to set the time base divider outputs to
11
all 9's".
5.47
The output of the time base divider chain, is taken from JC12a to the clock input
(pin 1) of IC3a on the Amplifier and High Speed Decade Assembly.
5.48
IC3a is a divide-by-two package which divides the clock input from JC12a on the
Control Assembly to provide a logic '1' output at Q for the duration of the main
gate period. This is applied to the
J
and K inputs of JC3b.
5.49
When the gate time has expired the Q output of JC3a goes to logic '0' closing
IC3b and stopping the count.
5-7
9057/9059
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