AMD Xilinx VCU128 User Manual page 21

Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd)
FPGA (U1) Pin
BF45
BE44
BF46
BE45
BE46
BD41
BP32
BP29
BP31
BP28
BN32
BM30
BN31
BL30
BN29
BN30
BM28
BL32
BP34
BN34
BK33
BL31
BL33
BM33
BK31
BL35
BM35
BM34
BJ34
BG35
BH34
BH35
BJ33
BF35
BG34
BF36
BK34
BK35
UG1302 (v1.2) May 6, 2022
VCU128 Board User Guide
Schematic Net
I/O Standard
Name
PL_DDR4_DQ29 POD12_DCI
PL_DDR4_DQ30 POD12_DCI
PL_DDR4_DQ31 POD12_DCI
PL_DDR4_DQS3_T DIFF_POD12_DCI
PL_DDR4_DQS3_C DIFF_POD12_DCI
PL_DDR4_DM3_B DIFF_POD12_DCI
PL_DDR4_DQ32 POD12_DCI
PL_DDR4_DQ33 POD12_DCI
PL_DDR4_DQ34 POD12_DCI
PL_DDR4_DQ35 POD12_DCI
PL_DDR4_DQ36 POD12_DCI
PL_DDR4_DQ37 POD12_DCI
PL_DDR4_DQ38 POD12_DCI
PL_DDR4_DQ39 POD12_DCI
PL_DDR4_DQS4_T DIFF_POD12_DCI
PL_DDR4_DQS4_C DIFF_POD12_DCI
PL_DDR4_DM4_B POD12_DCI
PL_DDR4_DQ40 POD12_DCI
PL_DDR4_DQ41 POD12_DCI
PL_DDR4_DQ42 POD12_DCI
PL_DDR4_DQ43 POD12_DCI
PL_DDR4_DQ44 POD12_DCI
PL_DDR4_DQ45 POD12_DCI
PL_DDR4_DQ46 POD12_DCI
PL_DDR4_DQ47 POD12_DCI
PL_DDR4_DQS5_T DIFF_POD12_DCI
PL_DDR4_DQS5_C DIFF_POD12_DCI
PL_DDR4_DM5_B POD12_DCI
PL_DDR4_DQ48 POD12_DCI
PL_DDR4_DQ49 POD12_DCI
PL_DDR4_DQ50 POD12_DCI
PL_DDR4_DQ51 POD12_DCI
PL_DDR4_DQ52 POD12_DCI
PL_DDR4_DQ53 POD12_DCI
PL_DDR4_DQ54 POD12_DCI
PL_DDR4_DQ55 POD12_DCI
PL_DDR4_DQS6_T DIFF_POD12_DCI
PL_DDR4_DQS6_C DIFF_POD12_DCI
Chapter 3: Board Component Descriptions
Component Memory
Pin # Pin Name
H8 DQ5
J3 DQ6
J7 DQ7
G3 LDQS_T
F3 LDQS_C
E7 NF/LDM_B/LDBI_B
G2 DQ0
F7 DQ1
H3 DQ2
H7 DQ3
H2 DQ4
H8 DQ5
J3 DQ6
J7 DQ7
G3 LDQS_T
F3 LDQS_C
E7 NF/LDM_B/LDBI_B
G2 DQ0
F7 DQ1
H3 DQ2
H7 DQ3
H2 DQ4
H8 DQ5
J3 DQ6
J7 DQ7
G3 LDQS_T
F3 LDQS_C
E7 NF/LDM_B/LDBI_B
A3 DQ8
B8 DQ9
C3 DQ10
C7 DQ11
C2 DQ12
C8 DQ13
D3 DQ14
D7 DQ15
B7 UDQS_T
A7 UDQS_C
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Ref. Des.
U18
U18
U18
U18
U18
U18
U73
U73
U73
U73
U73
U73
U73
U73
U73
U73
U73
U19
U19
U19
U19
U19
U19
U19
U19
U19
U19
U19
U18
U18
U18
U18
U18
U18
U18
U18
U18
U18
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