Analog Output; Digital I/O; Trigger Input; Sync I/O - Measurement Computing USB-7204 User Manual

USB-7204 User's Guide
The table below shows some possible inputs and the expected results.
CHHI
–20 V
–15 V
–10 V
–10 V
0 V
0 V
+10 V
+10 V
+15 V
+20 V

Analog output

You can connect up to two analog output connections to screw terminal pins 13 and 14 (
). Each channel can be paced individually at rates up to 10,000 updates per second. Both channels can be
OUT 1
paced simultaneously using the same time base at 5000 updates per channel. The 0-4.096 V output range
provides a convenient 1 mV per LSB when setting the output voltage levels.

Digital I/O

The USB-7204 has two eight-bit ports (
configurable as either input or output.
Pull up/down configuration
The digital pins are configurable via jumpers for pull-up to USB +5 V (HI) or pull-down to ground (LO).
Jumper JP2 configures Port 0, and JP1 configures Port 1. On power up and reset the DIO pins are configured as
input and pulled by JP1/JP2.
When configured for input, the digital I/O terminals can be used to detect the state of any TTL level input.
For more information on digital signal connections
For more information on digital signal connections and digital I/O techniques, refer to the Guide to DAQ Signal
Connections (available on our web site at www.mccdaq.com/signals/signals.pdf).

Trigger input

The digital trigger input (
This pin is internally connected to the TRIG_IN pin on the Trigger/Sync connector (see page 11).

SYNC I/O

The terminal is a bidirectional I/O signal that can be configured as an input or an output (default):
SYNC

Configure as an external clock input to externally pace the A/D conversions from an external source or
another USB-7204. The SYNC terminal supports TTL-level input signals of up to 50 kHz.
When used as a clock input, the SYNC pin operates in one of two modes – slave or gated slave.
o
In slave mode, the USB-7204 ignores the first clock pulse in order to ensure adequate setup time. Use
this mode when the USB-7204 is being paced from a continuous clock source, such as a generator.
Sample inputs and differential results
CHLO
0 V
+5 V
0 V
+10 V
+10 V
+20 V
–10 V
0 V
–5 V
0
to
Port 0 Bit 0
Figure 8. Jumper JP0 and JP1 configuration
) lets you start an acquisition when a signal's rising or falling edge is detected.
TRIG_IN
Result
Invalid
Invalid
–10 V
–20 V
–10 V
-20 V
+20 V
+10 V
+20 V
+20 V
to and to
Bit 7 Port 1 Bit 0
15
Functional Details
and
D/A OUT 0 D/A
to ). Each port is
Bit 7