Sdio Interfaces - Quectel AF55C Hardware Design

⚫
For PCIe signal traces, the maximum length of each differential data pair (Tx/Rx/REFCLK) is
recommended to be less than 300 mm, and each differential data pair matching should be less than
0.7 mm.
⚫
Spacing to all other signals is four times the trace width.
⚫
Do not route signal traces under crystals, oscillators, magnetic devices, or RF signal traces. It is
important to route the PCIe differential traces in inner-layer of the PCB and surround the traces with
ground on that layer and with ground planes above and below.
3.5.3. SDIO Interfaces*
The following table shows the pin definition of SDIO interfaces.
default.
Table 8: Pin Definition of SDIO Interfaces
Pin Name Pin No.
SDIO_CMD 1
SDIO_CLK 47
SDIO_DATA0 2
SDIO_DATA1 4
SDIO_DATA2 50
SDIO_DATA3 49
The following figure shows the SDIO interface connection between the module and the host.
AF55C_Hardware_Design
I/O Description
DIO SDIO command
DI SDIO clock
DIO SDIO data bit 0
DIO SDIO data bit 1
DIO SDIO data bit 2
DIO SDIO data bit 3
Automotive Wi-Fi&Bluetooth Module Series
SDIO is optional and is not supported by
Comment
SDIO is optional and is not
supported by default.
Requires impedance of 50 Ω.
If unused, keep them open.
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