Quectel AF55C Hardware Design page 22

PCIE_TX_M
PCIE_RX_P
PCIE_RX_M
PCIE_CLKREQ_N
PCIE_RST_N
PCIE_WAKE_N
The following figure shows the PCIe interface connection between the module and the host.
PCIE_CLKREQ_N
PCIE_WAKE_N
PCIE_RST_N
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_TX0_M
PCIE_TX0_P
PCIE_RX0_M
PCIE_RX0_P
HOST
To ensure the signal integrity of PCIe interfaces, C1 and C2 should be placed close to the HOST, and C3
and C4 should be placed close to the module. The extra stubs of traces must be as short as possible.
Reserve R6, R7 and C5 to C10 for impedance matching.
The following principles of PCIe interface design should be complied with to meet PCIe Gen 2
specifications.
⚫
It is important to route the PCIe signal traces as differential pairs with ground surrounded. And the
differential impedance is 100 Ω ± 10 %.
AF55C_Hardware_Design
7 AO PCIe transmit (-)
56 AI PCIe receive (+)
11 AI PCIe receive (-)
12 DO PCIe clock request
14 DI PCIe reset
13 DO PCIe wake up
VDD_IO
R1 R2 R3
49.9 Ω
100K 100K
C1
100 nF
C2
100 nF
C5 C6
NM_1.5 pF NM_1.5 pF
Figure 5: PCIe Interface Connection
Automotive Wi-Fi&Bluetooth Module Series
R4 R5
49.9 Ω
NM
R6
0 Ω
R7
0 Ω
C3
100 nF
C4
100 nF
C9 C10
NM_1.5 pF NM_1.5 pF
C7
NM_1.5 pF
Active low.
PCIE_CLKREQ_N
PCIE_WAKE_N
PCIE_RST_N
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_RX_M
PCIE_RX_P
PCIE_TX_M
PCIE_TX_P
AF55C
C8
NM_1.5 pF
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