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Epiq Solutions Sidekiq X2 Hardware User Manual

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Sidekiq™ X2
RF Transceiver • High Performance
HARDWARE USER MANUAL
V1.0 - NOVEMBER 11, 2020

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Summary of Contents for Epiq Solutions Sidekiq X2

  • Page 1 Sidekiq™ X2 RF Transceiver • High Performance HARDWARE USER MANUAL V1.0 - NOVEMBER 11, 2020...
  • Page 2 Sidekiq™ X2 | Hardware User Manual CHANGELOG Revision Date Description Author 2017-08-10 Pre-release draft, initial version Barry L 2017-09-07 Subtandital updates in content; Added full pin map; Added Rx pre-select filter plot Barry L 2017-09-15 Updates after internal review; ready for public release Barry L Updated sections 7.1, 7.3, 8, 8.7, 8.8, 10.2, 10.3, 11, table12.
  • Page 3 Epiq Solutions is disclosing this document (“Documentation”) as a general guideline for development. Epiq Solutions expressly disclaims any liability arising out of your use of the Documentation. Epiq Solutions reserves the right, at its sole discretion, to change the Documentation without notice at any time. Epiq Solutions assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 4: Table Of Contents

    ..................42 Basic Usage the Sidekiq X2 Thunderbolt 3 Platform...
  • Page 5 ..................43 Accessing JTAG on the Sidekiq X2 Thunderbolt 3 Platform .

  • Page 6: Introduction

    RF platform development cycle. Sidekiq X2 can interface to any FMC HPC host system, where an FPGA and additional follow on processing would be executed. Epiq Solutions provides an FPGA reference design as well as software drivers, libraries, and test applications to demonstrate the usage of Sidekiq X2 interfaced to a COTS FMC host platform with a PCIe interface to a host computing system.

  • Page 7: Legal Considerations

    Legal Considerations LEGAL CONSIDERATIONS The Sidekiq X2 is distributed all over the world. Each country has its own laws governing reception and transmission of radio frequencies. Each user of Sidekiq X2 and associated software is solely responsible for insuring that it is used in a manner consistent with the laws of the jurisdiction in which it is used.

  • Page 8: Proper Care And Handling

    Each Sidekiq X2 card is fully tested by Epiq Solutions before shipment, and is guaranteed functional at the time it is received by the customer, and ONLY AT THAT TIME. Improper use of the Sidekiq X2 card can cause it to become non-functional. In particular, a list of actions that may cause damage to...

  • Page 9: References

    Sidekiq™ X2 | Hardware User Manual References REFERENCES 1. Sidekiq X2 Product Page https://epiqsolutions.com/rf-transceiver/sidekiq-x2 2. Epiq Solutions Support Page https://support.epiqsolutions.com 3. VITA website https://www.vita.com 4. Analog Devices' AD9371 Wideband Transceiver Product Page http://www.analog.com/en/products/rf-microwave/integrated-transceivers-transmitters- receivers/wideband-transceivers-ic/ad9371.html 5. HiTech Global's Product Page for the HTG-K800 FPGA PCIe Carrier Card http://www.hitechglobal.com/Boards/Kintex-UltraScale.htm...

  • Page 10: Terms And Definitions

    Low Pin Count (a variant of the VITA 57.1 electrical interface) Megahertz MMCX Micro-Miniature Coaxial RF Connector ObsRx Observation Receiver Personal Computer Platform Development Kit Pulse Per Second Radio Frequency Receive Software Development Kit Software Defined Radio Sub-Miniature push-on RF connector Secure SHell Epiq Solutions Proprietary Page 10...
  • Page 11 Temperature Compensated Crystal Oscillator Transmit UART Universal Asynchronous Receiver Transmitter Universal Serial Bus The standards body governing a variety of electro-mechanical specifications for computing systems (see [3] for VITA details). Table 1: Terms and Definitions Epiq Solutions Proprietary Page 11...

  • Page 12: Hardware Overview

    RF pre-select filtering on the RF receivers, support external synchronization inputs, and other features only found on Sidekiq X2. The key highlights of Sidekiq X2 are enumerated below: VITA 57.1 FMC compliant card providing a high pin count (HPC) interface...
  • Page 13 Sidekiq™ X2 | Hardware User Manual Hardware Overview Figure 1: Sidekiq X2 card (with heatsink / RF shield installed) Epiq Solutions Proprietary Page 13...
  • Page 14 Sidekiq™ X2 | Hardware User Manual Hardware Overview Figure 2: Sidekiq X2 block diagram Epiq Solutions Proprietary Page 14...

  • Page 15: Hardware Specification

    75 MHz to 6 GHz, able to capture 1 MHz to 6 GHz Tuning Step Size 2.3 Hz Tuning Time ~ 1 ms to 2.5 ms, contact Epiq Solutions' support [2] for more detailed information Typical Noise Figure 6-8 dB below 3 GHz, 8-10 dB above 3 GHz Spurious-Free Dynamic Range ~ 70 –...

  • Page 16: Clock/Synchronization Specification

    ObsRx port Tuning Step Size 2.3 Hz Tuning Time ~ 1 to 2.5 ms, contact Epiq Solutions' support [2] for more detailed information Gain Control Range 0 to 42 dB, 1 dB steps Tx1: +10 dBm to +15 dBm (<3 GHz) Max RF Transmit Output +3 dBm to +10 dBm (>3 GHz)
  • Page 17 -55 deg C to +125 deg C (+/- 2 deg C resolution) P/N: Texas Instruments TMP100 FMC (12P0V) +12 V FMC (P3V3) +3.3 V FMC Vadj Support 1.8V or 2.5V Table 5: hardware specification Figure 3: Rx pre-select filter passband plot (filtering used on Rx1, Rx2, and ObsRx) Epiq Solutions Proprietary Page 17...

  • Page 18: Hardware Interfaces

    Hardware Interfaces HARDWARE INTERFACES Sidekiq X2 provides is a standard VITA 57.1 compliant FMC card, and thus has a specific set of externally accessible hardware interfaces that are available to a user when the card is integrated into a system. Each of these hardware interfaces are enumerated in Figure 4, and are defined below.

  • Page 19: J2 (Rx1)

    The 10 MHz Input port is an SSMC jack connector that accepts an external 10 MHz input signal for the purpose of phase locking the on board reference clock. The acceptable signal level for this external 10 MHz input is between -5 dBm and +10 dBm. By default, Sidekiq X2 has an internal Epiq Solutions Proprietary...

  • Page 20: Pps Input

    0.85V and 5V, dependent on Vadj (+1.8V / +2.5V). This PPS signal is used by the Sidekiq X2 FPGA reference design to latch the digital timestamp of when the PPS edge occurs in the FPGA, and can then be queried by the libsidekiq software API.

  • Page 21: Supplemental Heat Transfer Surface

    This area surrounding the edge of the card is defined in the VITA 57.1 specification for the purpose of thermal relief, and can be used in conduction cooled deployments. For convection cooled deployments with the appropriate airflow moving over the RF shield + heatsink, this supplemental heat transfer surface is unused. Epiq Solutions Proprietary Page 21...

  • Page 22: Fmc Pin Map

    FMC specification, and more importantly, the Sidekiq X2 FPGA reference design delivered with the Sidekiq X2 PDK. Epiq Solutions provides support for Sidekiq X2 when used in conjunction with the Sidekiq X2 FPGA reference design and associated libsidekiq software library.
  • Page 23 VADJ1 Vadj carrier card (1.8V to from carrier to mezzanine 2.5V) Vadj supply set by Adjustable voltage level power VADJ0 Vadj carrier card (1.8V to from carrier to mezzanine 2.5V) 12P0V1 Main 12V power input Epiq Solutions Proprietary Page 23...
  • Page 24 LED I2C serial Vadj, LA03_N User defined signal on Bank A FMC_SDA data line In/Out AD9528 Vadj, LA04_P User defined signal on Bank A FMC_AD9528_CS_N SPI chip select LA04_N User defined signal on Bank A Epiq Solutions Proprietary Page 24...
  • Page 25 External SYSREF input clock User defined LVDS, LA11_N signal on Bank AD9528_SYSREF_IN_N External SYSREF input clock User defined Enables the 153.6 MHz reference VCXO Vadj, LA12_P signal on Bank FMC_VCXO_153M6_EN (high=153.6 MHz VCXO enabled, low=100 MHz VCXO enabled) Epiq Solutions Proprietary Page 25...
  • Page 26 Bank A User defined signal LA21_P on Bank A User defined signal LA21_N on Bank A User defined signal Vadj, LA22_P FMC_PLL1_RESET_N RF front end SPI reset for Rx1 and Rx2 on Bank A Epiq Solutions Proprietary Page 26...
  • Page 27 RF front end SPI chip select for ObsRx Vadj, LA31_N FMC_PLL2_CS_N Bank A and Tx1 (active low) User defined signal on Vadj, LA32_P FMC_MYK_PWR_EN Enable AD9371 power supplies Bank A User defined signal on LA32_N Bank A Epiq Solutions Proprietary Page 27...

  • Page 28: Fmc High Pin Count (Hpc) Section

    User defined signal on Bank A LA33_N User defined signal on Bank A Table 6: FMC Low Pin Count Pinout FMC HIGH PIN COUNT (HPC) SECTION FMC Signal Sidekiq X2 Logic Standard, FMC Description Description Name Net Name I/O Type...
  • Page 29 Gigabit interface diff pair driven from DP5_M2C_N mezzanine to host Gigabit interface diff pair driven from DP6_M2C_P mezzanine to host Gigabit interface diff pair driven from DP6_M2C_N mezzanine to host Gigabit interface diff pair driven from DP7_M2C_P mezzanine to host Epiq Solutions Proprietary Page 29...
  • Page 30 User defined signal on Bank A, uses reference voltage Vadj, HA05_P MYK_GPIO8 referenced to on pin VREF_A_M2C In/Out Vadj AD9371 GPIO User defined signal on Bank A, uses reference voltage Vadj, HA05_N MYK_GPIO15 referenced to on pin VREF_A_M2C In/Out Vadj Epiq Solutions Proprietary Page 30...
  • Page 31 VREF_A_M2C User defined signal on Bank A, uses reference HA15_N voltage on pin VREF_A_M2C User defined signal on Bank A, uses reference AD9371 GPIO Vadj, HA16_P MYK_GPIO16 voltage on pin VREF_A_M2C referenced to Vadj In/Out Epiq Solutions Proprietary Page 31...
  • Page 32 User defined signal on Bank A, uses reference voltage HB01_P on pin VREF_B_M2C User defined signal on Bank A, uses reference voltage HB01_N on pin VREF_B_M2C User defined signal on Bank A, uses reference voltage HB02_P on pin VREF_B_M2C Epiq Solutions Proprietary Page 32...
  • Page 33 User defined signal on Bank A, uses reference voltage on pin VREF_B_M2C HB17_N_CC User defined signal on Bank A, uses reference voltage on pin VREF_B_M2C HB18_P User defined signal on Bank A, uses reference voltage on pin VREF_B_M2C Epiq Solutions Proprietary Page 33...
  • Page 34 User defined signal on Bank A, uses reference voltage on pin VREF_B_M2C HB21_P User defined signal on Bank A, uses reference voltage on pin VREFBM2C HB21_N User defined signal on Bank A, uses reference voltage on pin VREF_B_M2C Table 7: FMC High Pin Count Pinout Epiq Solutions Proprietary Page 34...

  • Page 35: Basic Usage In A Host System

    BASIC USAGE IN A HOST SYSTEM HOST SYSTEM COMPATIBILITY Sidekiq X2 is expected to be deployed into a host system that adheres to a general architecture in order to utilize the core FPGA reference design and associated libsidekiq software API. This general architecture is shown in Figure 5 below.

  • Page 36: Operating System Compatibility

    Basic Usage in a Host System In an alternate deployment scenario, Sidekiq X2 can be interfaced to a 3U VPX carrier card that hosts an integrated FPGA + CPU in a single chip, such as the Xilinx Zynq Ultrascale+ SoC. In this scenario, both the FPGA fabric required to execute the Sidekiq X2 FPGA reference design and the multi-core ARM CPU running the libsidekiq software library are located on a single device (i.e., the...

  • Page 37: Thermal Dissipation

    For a standard convection cooled deployment, the required air flow over the heatsink on the card is TBD LFM. Sidekiq X2 uses components that are rated for operation to +85 deg C, and thus the end user must ensure that the temperature reported by the on-board temperature sensor does not exceed +85 deg C.
  • Page 38 Sidekiq™ X2 | Hardware User Manual Basic Usage in a Host System Table 9: Sidekiq X2 component power consumption The side with the FMC connector is designated "Top". Component locations are shown below. Figure 8: Sidekiq X2 Top Epiq Solutions Proprietary...

  • Page 39: Jtag Access On Sidekiq

    Sidekiq™ X2 | Hardware User Manual Basic Usage in a Host System Figure 9: Sidekiq X2 Bottom The thermal gap pad material used on the X2 RFIC (U11) is Bergquist Gap Pad P/N: GPVOUS- 0.040-00 The thermal pad is 0.472" x 0.472" x 0.040" thick and is compressed around 50%.

  • Page 40: Sidekiq X2 Mechanical Outline

    Sidekiq X2 Mechanical Outline SIDEKIQ X2 MECHANICAL OUTLINE A dimensioned mechanical drawing of Sidekiq X2 in convection cooled form is shown in Figure 9. In addition, a 3D model (in STP format) is also available. Please contact Epiq Solutions for this model.

  • Page 41: Sidekiq X2 Thunderbolt 3 Platform

    Sidekiq X2 + HTG-K800 PCIe card installed into the Thunderbolt 3 chassis and connected to a host laptop is shown in Figure 9. Figure 10: Sidekiq X2 + HTG-K800 FPGA host board installed into a Thunderbolt 3 chassis, interfaced to a laptop via a Thunderbolt 3 cable...

  • Page 42: Basic Usage The Sidekiq X2 Thunderbolt 3 Platform

    Thunderbolt 3 platform that ships with the PDK: Step 1. With the Sidekiq X2 Thunderbolt 3 platform powered on first (using the provided DC power brick for the Thunderbolt 3 chassis), connect the TB3 chassis to the laptop with the provided TB3 cable and power on the laptop last.
  • Page 43 Figure 10 below. Note: it is critical that the user exercise proper electrical safety measures and ESD protection when interacting with open frame electronics. Failure to do so can permanently damage both the Sidekiq X2 card as well as the HTG-K800 FPGA board.
  • Page 44 Sidekiq™ X2 | Hardware User Manual Sidekiq X2 Thunderbolt 3 Platform Figure 11: JTAG port access on the Sidekiq X2 Thunderbolt 3 platform Once the JTAG cable is installed, the Thunderbolt 3 chassis cover can be carefully replaced, as shown in Figure 11, with the JTAG cable coming through the front panel of the unit. This ensures that the airflow from the internal fans is properly ducted over the critical components including Sidekiq X2.
  • Page 45 Sidekiq™ X2 | Hardware User Manual Sidekiq X2 Thunderbolt 3 Platform Figure 12: Thunderbolt 3 chassis closed up with Xilinx JTAG interface installed With the Thunderbolt 3 chassis reassembled, the user can resume normal usage of the system. Epiq Solutions Proprietary...
  • Page 46 Sidekiq™ X2 | Hardware User Manual Appendix A - Sidekiq X2 Statement of Volatility APPENDIX A - SIDEKIQ X2 STATEMENT OF VOLATILITY Model Sidekiq X2 Part Number ES020-104 Manufacturer Epiq Solutions 3740 Industrial Avenue Address Rolling Meadows, IL 60008 Table 10: Model, Part Number, and Manufacturer Info...
  • Page 47 Appendix B - Failure Rate & MTBF APPENDIX B - FAILURE RATE & MTBF Listed below is the Failure Rate and MTBF for the ES020-211-C Sidekiq X2 Assembly with Preselect Filters and SSMC RF Connectors. The Calculations are derived from Relyence Reliability Software and based off a fixed/ground/controlled operating environment with an ambient temperature of 25°C.

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Es020-211-c

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