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Epiq Solutions Sidekiq X2 Development Manual

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Sidekiq X2/X4 PDK
FPGA Development Manual
Release 3.17.1
Jan 27, 2023

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Summary of Contents for Epiq Solutions Sidekiq X2

  • Page 1 Sidekiq X2/X4 PDK FPGA Development Manual Release 3.17.1 Jan 27, 2023...

  • Page 2: Table Of Contents

    ........21 References ©2023 Epiq Solutions, All Rights Reserved...
  • Page 3 ........2.2 Sidekiq X2/X4 User Application Block Diagram .
  • Page 4 ........17 ©2023 Epiq Solutions, All Rights Reserved...
  • Page 5 Documentation without notice at any time. Epiq Solutions assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Epiq Solutions expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
  • Page 6 Upgrade to 8 lane PCIe for HTG-K800 and HTG-K810. Fix for starting/stopping streaming on a 1PPS edge. 04/06/2021 3.15.0 Fix Tx Timestamp dropped packets after late bug. Fix JESD Tx bug. continues on next page ©2023 Epiq Solutions, All Rights Reserved...
  • Page 7 Increase rx_dma_meta_fifo sizes to increase throughput rate in Rx low latency mode. X4 xcku115 Only, Add 1 ms POR to the x4 xcku115 (htgk8100 and htgk810) PCIe module X4 Only, Update JESD Rx path for deterministic latency ©2023 Epiq Solutions, All Rights Reserved...

  • Page 8: Overview

    1.3 Proper Care and Handling The SidekiqX2 or SidekiqX4 unit is fully tested by Epiq Solutions before shipment, and is guaranteed functional at the time it is received by the customer, and ONLY AT THAT TIME. Improper use of the SidekiqX2 or SidekiqX4 unit can cause it to become non-functional.

  • Page 9: Terms And Definitions

    In addition, the details of the hardware itself and system design of the unit is outside the scope of this document. For more details about the hardware, please download and review the Sidekiq X2 Hardware User’s Manual [4] or the Sidekiq X4 Hardware User’s Manual [6].

  • Page 10: Fpga Reference Design

    SidekiqX4 (not shown in the diagram) is the same as SidekiqX2 except that it has three additional channels (Rx1, Rx2, and ObsRx) coming from the second RFIC chip and two additional JESD modules (JESD204 chC and chD) for interfacing these channels to the user_app. ©2023 Epiq Solutions, All Rights Reserved...

  • Page 11: Fpga Top Level

    Epiq Solutions Proprietary 2.2: FPGA Top Level Fig. 2.1: Sidekiq X2/X4 Simplified Block Diagram 2.2 FPGA Top Level The Top Level block, sidekiq_x2_top (sidekiq_x4_top for the X4) is a wrapper containing the top level RTL and all submodules. This section will serve to describe each block’s functions and use. Sections that have more significant impact on a PDK user will be discussed in greater detail.

  • Page 12: Timestamp Module

    The user_app structure is designed to allow for portable signal processing blocks between multiple Epiq SDR platforms, including all Sidekiq variants. This allows end users to share user_app modules between platforms, including future platforms, with minimal rework required. ©2023 Epiq Solutions, All Rights Reserved...

  • Page 13: User Application Interfaces

    This design has multiple logical data channels. The channels use the notation <H> to indicate the software handle associated with the channel. <H> can have values ‘a1’, ‘a2’, and ‘b1’ for Sidekiq X2, and ‘a1’, ‘a2’, ‘b2’, ‘c1’, or ‘d1’ for Sidekiq X4.

  • Page 14: System Clocks And Resets

    The system control and status interface is comprised of signals relating to the overall system. The signals are de- 2.5. reg_rx_<H> is a 32-bit bus from the SW register interface. The bus contains individual status scribed in Table 2.6. Note that not all bits of reg_rx_<H> are defined. flags described in Table ©2023 Epiq Solutions, All Rights Reserved...

  • Page 15: Software Register Interface

    After a read request is issued, indicated by a pulse on reg_rd_en, the register interface shall place the read data on the reg_rd_data bus and assert the reg_rd_rd for 1 host_clk clock cycle to indicate the read data is valid. ©2023 Epiq Solutions, All Rights Reserved...

  • Page 16: Software Register Interface

    Register Read Ready. VAR_LATENCY_REG_RD=1 mode only. Handshaking pulse indicating the register read data is available on the bus. Fig. 2.3: Register Write Interface Timing Diagram Fig. 2.4: Register Read Interface Timing Diagram (VAR_LATENCY_REG_RD=0) ©2023 Epiq Solutions, All Rights Reserved...

  • Page 17: Test Memory Interface

    There is also an example software test application that demonstrates how to set up and exercise this feature using the API. The various tx_test_mem modules are instantiated at the bottom of user_app.v. The various top level user_app ports associated with this functionality are described in Table 2.8. ©2023 Epiq Solutions, All Rights Reserved...

  • Page 18: Rfic Control Interface

    The signals of GPIO interface are described in Table 2.9. The second, is the RFIC’s SPI Bus interface. The signals 2.10. Both the GPIO and SPI interfaces are synchronous to the host_clk. of SPI Bus interface are described in Table ©2023 Epiq Solutions, All Rights Reserved...

  • Page 19: Rfic Receive Data Interface

    Each counter continually increments as long as its associated clock is running. The counters can be reset using a software-programmable PPS based reset or by user logic. Fig. 2.6 shows the relationship between the sample clock, data buses, and free running counter. ©2023 Epiq Solutions, All Rights Reserved...

  • Page 20: Rfic Transmit Data Interface

    Quadrature-phase dual lane data path. tx_rd_en_in_<H> Flag indicating tx data interface is ready for data. This flag must be high prior to asserting tx_rd_en_out<H>. tx_dac_en_out_<H> Flag indicating tx_i_<H> and tx_q_<H> are valid data. ©2023 Epiq Solutions, All Rights Reserved...

  • Page 21: Rx Transport Dma Interface

    The Tx transport DMA interface is responsible for moving data from firmware running on the host processor to the user application. During times when there is not any transmit data available to be sent, the JESD Tx lanes will send all zeros to the RFIC. ©2023 Epiq Solutions, All Rights Reserved...

  • Page 22: User Register Interface Module

    They are driven by host_clk. The user may rename, add, or delete as desired to interface with user logic. If further register customization is desired, follow the template found in the source code. The provided read/write (software driven) registers and read-only registers are enumerated in Table 2.15. ©2023 Epiq Solutions, All Rights Reserved...

  • Page 23: User Registers

    8 and 9 synchronization logic as a template. Alternatively, the user may synchronize individual signals or buses to a specific clock domain using save clock domain crossing techniques. ©2023 Epiq Solutions, All Rights Reserved...

  • Page 24: Building And Debugging

    HiTech Global HTG-K800. (see [1]) sidekiq_x4_xcku115_pdk_<V>.bin XCKU115-2FLVA1517E SidekiqX4 I/Q streaming reference design targeting the HiTech Global HTG-K800. (see [1]) sidekiq_x4_ams_pdk_<V>.bin XCKU060-2FFVA1517E SidekiqX4 I/Q streaming reference design targeting the Annapolis Micro Systems. WB3XZD carrier. (see [8]) ©2023 Epiq Solutions, All Rights Reserved...

  • Page 25: Custom User Applications

    If you would like more information on how the incremental compile flow works, please consult the appropriate Xilinx documentation for an explanation of how to properly use this feature. For batch (non-GUI) mode: $ vivado -mode batch -source vivado_build.tcl ©2023 Epiq Solutions, All Rights Reserved...

  • Page 26: Annapolis Micro Systems Build Steps For The Wszkvup_Vpx3U_Iope_Dram Platform

    If this is desirable, the user must set the AMS_LIB_ROOT environment variable using: $ export AMS_LIB_ROOT= pwd If AMS_LIB_ROOT is not set, the build script assumes the library is located in the projects root folder as shown in Fig. 3.1. ©2023 Epiq Solutions, All Rights Reserved...

  • Page 27: Programming The Flash

    A JTAG port is provided to facilitate debug for PDK customers. Xilinx’s Chipscope application can be used to view internal FPGA signaling. Full Chipscope capabilities and use are beyond the scope of this document. For more information, see the Sidekiq X2 Hardware User’s Manual [4] or the Sidekiq X4 Hardware User’s Manual [6]. Caution: Xilinx programmers can be connected to the JTAG port, however the user should not use JTAG to program a bitstream.

  • Page 28: Appendix: Top Level Rtl Design Information

    The top level RTL contains a jesd_mapping module, as well as a jesd204_chA_support and jesd204_chB_support for Sidekiq X2 and a jesd204_chA_support, jesd204_chB_support, jesd204_chC_support, and jesd204_chD_support for Sidekiq X4. Each jesd204_chX_support module contains two JESD PHYs that interface to a single Tx/Rx JESD serial interface, as well as the JESD core logic needed to support those two PHY interfaces.

  • Page 29: References

    [2] Epiq Solutions Inc. Epiq solutions support website. URL: http://www.epiqsolutions.com/support. [3] Epiq Solutions Inc. Sidekiq software development manual. URL: http://www.epiqsolutions.com/support. [4] Epiq Solutions Inc. Sidekiq x2 hardware user’s manual. URL: http://www.epiqsolutions.com/support. [5] Epiq Solutions Inc. Sidekiq x2 product page. URL: http://www.epiqsolutions.com.

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