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The
output
of
ICS
becomes
positive
turning
Q10
and
Q11
on.
Thus
the
single
sawtooth output
is
created.
When
the
Model 144
is
in
the
SWP
HOLD
mode,
emitters
of
Q26,
27,
and
28
are
tied
to
ground through
the
MODE
selector.
Therefore, those
transistors
and
the zero detector
are
not
in
a part
of the operation.
It
is
also
to
be noted
that
the
peak
voltage reference
is
not switched
when
the
peak
voltage
is
detected.
In
the
standby
state,
when
the
trigger
input voltage
is
less
than the
trigger
level
setting,
the
gate
of
Q10
is
forced
to
ground.
The
current source
is
switched
off
and
the timing capacitor
is
discharged
through
QIO.
Therefore, the
output
of the
sawtooth
amplifier
isat
ground.
As
soon
as
the
trigger
input
overcomes
the
trigger
level
setting,
the
ground
signal at
the gate of
QIO
is
removed,
positive integration
takes place
and
the timing capacitor
is
charged
up
to
+5
volts.
When
Q24A
detects the
voltage,
Q12
turns
on
harder
and
begins to discharge the timing
capacitor.
As
soon
as
the capacitor voltage decreases,
Q24A
begins to turn
on
harder, forcing
Q14
to turn
on
and
Q12
to turn
off.
The
result
is
a
balanced condition
at
+5
volts
as
long
as
the
trigger
input
exceeds the
trigger
level
setting,
GCV
Amplifier
Generator
controlled voltage
(GCV)
is
provided
for
all
three
sweep
modes
of the
Model
144.
IC2
is
a
unity
gain inverting amplifier
which
converts the
VCG
amplifier
output
(0
to
—5
volts)
to
0
to
+5
volts.
Power
Supply
AC
voltage
is
coupled
from
the transformer
secondary
to
the bridge
rectifiers
CR1
through
CR8.
Filtering
is
pro-
vided
by
Cl, C2,
CIO, and C12.
Q9
is
connected and
operated
as a
zener reference
for
the
+15
V
supply. IC1
is
a
comparator
differential
amplifier
whose
output
is
used
to
drive
transistor
amplifier
Q4,
whose
output
at
the
collector
is
used
to
drive
a
Darlington
connected
pair
consisting
of
Q1
and Q2.
The
Darlington
connected
pair
provides
added
current
gain;
Q3
is
a
current
limiting device.
The
base voltage of
Q3
is
a
current
limiting device.
The
base voltage
of
Q3
is
biased
by
voltage divider
R5
and
R7
to
be
slightly
below +15
volts.
Therefore,
for
normal
operation
Q3
is
reverse biased
and no
current flows
through
its
collector.
However,
when
the
output
current
from
the
+15
volts
exceeds
a
certain
limit,
the voltage
drop
across
R12
will
increase
to
a
point
exceeding
the
total
voltage across
R5
plus
the base-emitter voltage of
Q3,
forward
biasing
Q3.
The
current
driving
the base
of
Q2
will
be
diverted to the collector of
Q3,
causing the
power
supply
voltage to
drop below normal
operating
voltage.
As
the
power
supply
voltage drops, voltage divider
R5
and
R7
has
more
effect
on
the base of
Q2;
eventually
turning
it
off
completely.
When
the overload condition
is
removed,
the
normal
condition
will
be
restored.
The
diode,
CR9,
across the input terminals
of IC1
pre-
vents
latch-up.
Potentiometer
R21
is
used
to calibrate the
+ 15
volt
supply.
The
—15
volt,
and
±28
volt supplies
have
similar circuitry.
The
—15
volt
supply
is
referenced to the
+15
volt
supply while
the
+15
volt
supply
is
referenced
to
the
—15
volts.
The
—28
volt
supply
is
referenced to the
—15
volts,
and
the
+28
volts
is
referenced to the
+15
volt
supply.
3-13
8/73
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