HP 3580A Operating And Service Manual page 64

Section IV
takes approximately 100 µsec. for the frequency ramp to
increase enough to increment the X-Axis A to D Converter
to state 1. In this case, only 17 µsec. have elapsed since the
beginning of the sweep so the output of the X-Axis A to D
Converter is still </J. When ClO goes low, the 8-bit word
from the Y-Axis A to D Converter is again written into
address r/J. This 8-bit word may be the same or may differ
from the one previously written into address
r/J.
Since the
Y-Axis A to D Converter detects and retains the peak value
of the video signal during each X-axis segment, the final
word written into address r/J will represent the peak
amplitude during the first segment. When Cl again goes
low, the Address Counter is incremented to state 1
(0000000001) and RAM address 1 is selected. When C9
goes high, the contents of address 1 are strobed into the
8-bit Latch. Since the RAM was cleared at the beginning of
the sweep and the X-Axis A to D Converter has not yet
incremented to state 1, addresses 1 through 1023 contain
all zeros. The output of the D to A Converter is, therefore,
0 V and the CRT trace at this point is at the bottom of the
screen.
4-135. As the sequence continues, the Address Counter is
incremented at 17 µsec. intervals by Clock C 1. During each
read phase of Cl, a new RAM address is selected and a new
8-bit word is strobed into the Latch, converted to de and
applied to the vertical deflection plates of the CRT. As a
result, all 1022 addresses are read and the display is swept
in approximately 17.4 msec.
4-136. At the end of the first display sweep, the frequency
ramp will be about + 0.81 V and only the first 174 RAM
addresses will be filled. Thus, almost six display sweeps will
have been made by the time the RAM is completely filled.
4-137. At the end of the 0.1 second single sweep, the
entire memory will be filled and the frequency ramp at the
input of the X-Axis A to D Converter will remain at+ 5 V.
At that time, the output of the X-Axis A to D Converter
will be 1111111111, corresponding to RAM address 1023.
During each write phase of Cl, an 8-bit word will be
written into address 1023. This is of no consequence
because the Address Counter resets the Display Ramp
Generator in state 1022 and addresses 1022 and 1023 are
not displayed. The Address Counter will continue to cycle,
the memory will be read and the display will be swept at a
17.4 msec. rate. The trace stored in memory will, therefore,
continue to be displayed until it is cleared or updated by a
new frequency sweep.
4-138. Clearing A Trace. When the CLEAR/WRITE button
is pressed, the following things take place:
a. The Y-Axis A to D Converter is held in the reset state
and its output is 00000000.
b. The RAM Address lines are switched to the Address
Counter during both the read and write phases of Cl.
4-20
Model 3580A
c. As the Address Counter scans the memory, all zeros
are written in each address and the entire memory is cleared
in 17.4 msec.
4-139. Store Function.
A major feature of the Digital
Storage Section is the "store function" which allows a trace
to be permanently stored in memory for future reference.
The permanently stored trace can be blanked from the
display and then recalled at any time for comparison with
the current or ''refresh" trace.
4-140. To permanently store a trace, the operator presses
the front panel STORE button. This initiates a sequence of
operations in which the trace currently in memory is
processed and reloaded into 512 of the 1024 memory
locations. The remaining half of the memory is used for the
refresh trace. To display both traces, the display sweep rate
is doubled to provide two 8.7 msec. sweeps. During the first
display sweep, the Address Counter scans the memory
locations containing the refresh trace. It then recycles and
scans the memory locations containing the permanently
stored trace. As a result, the two traces are displayed
alternately in a 17 .4 msec. period.
4-141. Figure 4-22 is an expanded block diagram showing
the additional circuitry needed to implement the store
function. A 4-state digital controller called the "Store
Function Controller" is used to direct the store operation.
The ASM chart for the Store Function Controller is shown
in Figure 4-23. Other elements used only for the store
function are the Store Multiplexer, the 8-Bit Adder and the
Write Control circuit.
4-142.
Store Multiplexer. The Store Multiplexer switches
the RAM Data Input lines between the Y-Axis A to D
Converter and the
"Q"
outputs of the 8-Bit Latch. The
switching inputs to the Store Multiplexer are the SFL and
TRA instructions from the Store Function Controller.
During normal operation, the SFL and TRA instructions
are not given and the RAM Data Input lines are always
connected to the Y-Axis A to D Converter. When the SFL
or TRA instruction is given during the store sequence, the
RAM Data Input lines are switched to the
"Q"
outputs of
the 8-Bit Latch and the Y-Axis A to D Converter is
disconnected.
4-143. 8-Bit Adder. In State 1 of the store sequence, the
Adder is used to compare the 8-bit word on the RAM Data
Output lines to the 8-bit word at the output of the Latch.
The comparison is made using one's compliment addition
i.e., the
"Q"
outputs of the Latch are the compliments of
the
"Q"
outputs. If the numerical value of the word at the
output of the RAM is greater than that of the word at the
output of the Latch, the "Carry" output of the Adder goes
high, supplying a ''Write Enable" command to the Write
Control circuit.
4-144.
Write Control Circuit. During normal operation,
the "Set" input to the write control
flip-fl~
is high,
forcing the
"Q".
output to be high. Clock ClO is then
present at the output of the NAND gate and data is written
into memory during each write phase of Clock Cl. When