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EN 20
5.
PB52.1HU LB
switch off the remaining DC/DC
converters
Switch POD-MODE and ON-MODE
3-th try?
I/O line high.
Yes
Blink Code as
error code
SP
- Channeldecoder type TDA10060
cannot be reloaded without reset
of the channeldecoder.
- Channeldecoder type TDA10048
can be reloaded without reset.
Channel decoder
No
TDA 10048?
Third try?
Log channel decoder error
Service Modes, Error Codes, and Fault Finding
Init Pacific according use case :
to be discussed with Stefan / SW if we will put this here or in
the display excel overview of Stefan or in .....
Enable the Pacific output by sending the PanelConfig.PanelOn
Yes
No
No
Yes
Initialize video processing IC 's
- PNX5050 in /82
- scaler EPLD
initialize AutoTV by triggering CHS AutoTV Init interface
Do not enter semi - standby state in case of an LPL
scanning backlight LCD set before 4s preheating timer has
elapsed.
Figure 5-5 "Off" to "Semi Stand-by" flowchart (part 3)
Power-ok display high ?
Yes
Reset the Pacific by pulling LOW the Pacific
hardware reset line during 100ms.
Release Pacific reset
and wait 200ms
Ping the Pacific through I²C
Pacific acknowledges ?
Yes
- lvds or CMOS input and output
- panel config...
to the Pacific in case of a DFI set
Start 4 seconds preheating timer in case of
an LPL scanning backlight LCD set .
Initialize audio according FMS information:
Download firmware into the channel
decoder
Downloaded
successfully ?
Yes
initialize tuner , Master IF and channel
decoder
Initialize source selection
Wait until Cpipe delivers a stable output
clock
Reset EPLD
Wait 100ms
Reset Pacific clock
Initialize Pacific or EPLD related Ambilight
settings (if applicable)
Initialize Ambilight with Lights off .
Semi-Standby
Log power-ok error and enter
No
protection
MP
No
No
Third Pacific boot retry?
Yes
Log Pacific error
This is needed here because the Pacific has to
deliver an output clock towards the DFI. Otherwise
the DFI cannot deliver ambilight functionality in the
lampadaire mode. The presence of the DFI can be
determined via the display option.
EPLD
and
Pacific
should
be reset
when a
stable
input
clock
become
s
available
at their
input.
:
H_17650_094c.eps
090826
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