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Summary of Contents for PLX Technology PEX8603
- Page 1 PEX8603 TQFP-AIC RDK PLX Technology Hardware Reference Manual PEX8603 TQFP-AIC Rapid Development Kit © PLX Technology, www.plxtech.com Page 1 of 23 05Mar13, Version 1.0...
- Page 2 This document contains PLX Confidential and Proprietary information. The contents of this document may not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc. PLX provides the information and data included in this document for your benefit, but it is not possible to entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured products.
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Page 3: Table Of Contents
PEX8603 TQFP-AIC RDK Table of Contents GENERAL INFORMATION ......................5 PEX8603 Features ..............................7 PEX8603 AIC RDK Features ..........................8 Getting Started ................................. 9 PEX8603 RDK HARDWARE ARCHITECTURE ................ 10 Architecture Block Diagram ..........................10 Board Components ..............................11 PEX8603 PCI Express Switch ..........................13 PCI Express Upstream Port Connection ...................... - Page 4 Hardware Strap Pins ............................. 22 Configuration Modules ............................22 Hardware Jumpers ..............................23 Figures Figure 1. PEX8603 RDK Front View ___________________________________________________________________________ 6 Figure 2. Getting Started ______________________________________________________________________________________ 9 Figure 3. RDK Architecture ____________________________________________________________________________________ 10 Figure 4. RDK Component Locations ____________________________________________________________________________ 12 Figure 5.
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Page 5: General Information
The PEX8603 TQFP RDK supports the use of one configuration module slot to provide flexibility in the routing of PCIe lane 1 to either the x4 PCIe edge connector or to one of the PCIe slots. The Configuration Module enables the RDK to support the following port configurations: Table 1. -
Page 6: Figure 1. Pex8603 Rdk Front View
TESTMODE1 TESTMODE0 TP21 TP32 TP27 GPIO0 I2C_ADDR2 I2C_ADDR1 I2C_ADDR0 TP25 R108 PROBE_MODE# SERDES_MODE_EN# PLL_BYPASS# TP34 TP24 FAST_BRINGUP# R109 DEBUG_SEL# GPIO1 GPIO2 GPIO3 Figure 1. PEX8603 TQFP RDK Front View © PLX Technology, www.plxtech.com Page 6 of 23 05Mar13, Version 1.0... -
Page 7: Pex8603 Features
PEX8603 TQFP-AIC RDK 1.1 PEX8603 Features The PEX 8603 supports the following features: • 3-Port PCI Express switch – 3 Lanes with integrated on-chip SerDes – Low-power SerDes (under 90 mW per Lane) – Fully Non-Blocking Switch architecture – Port configuration ... -
Page 8: Pex8603 Aic Rdk Features
14x14mm 128-lead TQFP package • Typical power – 0.8W 1.2 PEX8603 AIC RDK Features • PEX8603-AB PCI Express 3-port Gen 2 PCIE Switch • X4 Upstream goldfinger • Two downstream PCI Express x16 Slot Connectors • DIP Switches for hardware configuration of PEX8603 •... -
Page 9: Getting Started
PEX8603 TQFP-AIC RDK 1.3 Getting Started Figure 2. Getting Started Follow the following steps to use the RDK. 1) Plug board into x16 PCI Express slot on motherboard. 2) Check and set dipswitches for desired port configuration. 3) Check that the correct configuration module is plugged into the socket. -
Page 10: Pex8603 Rdk Hardware Architecture
PEX8603 TQFP-AIC RDK 2 PEX8603 RDK Hardware Architecture 2.1 Architecture Block Diagram X16 Connector(P5) X16 Connector(P3) EEPROM JTAG Lane2 Lane1 (U2) (JP1) PEX 8603 TQFP (JP2) (U1) Status LED RefClk Lane0 DIPSW Buffer (U8) X4 Card Edge(P2) PERST# Figure 3. RDK Architecture ©... -
Page 11: Board Components
Component Location Component Location PCI Express Slots (P3,P5) JTAG connector (JP1) Lane Good LEDs (D3,D4,D5,D6) PEX8603 Chip (Chip not installed in diagram) (U1) Power-on Reset Button (S2) PCIE Goldfinger (P2) PERST# Button (S1) Voltage Indicator LEDs (D9,D10,D11) I2C Connector (JP2) -
Page 12: Figure 4. Rdk Component Locations
PEX8603 TQFP-AIC RDK Not used for 8603 PEX8603 RDK Figure 4. RDK Component Locations © PLX Technology, www.plxtech.com Page 12 of 23 05Mar13, Version 1.0... -
Page 13: Pex8603 Pci Express Switch
The upstream x4 connector can be a x1 or x2 link connecting the PEX8603 to the add-in card male edge connector. The PEX8603 RDK can plug into x1 PCI Express slots by using a PCI Express lane converter, such as PCI Express X4-To-X1 Converter made by Adex Electronics. -
Page 14: Dipswitch Setting Tables
Table 3. SW1 Functions SW1 Functional Description Switch Position Settings L = x1 x1 x1 PORTCFG0 H = X2 x1 Used to select the PEX8603’s Port configuration. Default Setting = L L = Enables SMBUS Mode SMBUS_EN# H = Enables I... -
Page 15: Table 4. Sw2 Functions
GPIO0 Factory Test Only Default Setting = H Used to define the default value of the three least significant bits of the PEX8603 I2C/SMBus 7-bit Slave address. CADDR[2:0] C Lower Slave Address Bits Default Setting = LLL Table 5. SW3 Functions... -
Page 16: Power Circuitry
Voltage monitoring circuits are placed close to the PEX8603 chip. If the supplies are off 10% of their normal values, red LED(s) will be turned on to signal the potential voltage problem to the chip. Bypass capacitors, plane capacitors are used to filter out the voltage noise. -
Page 17: I2C/Smbus Interface
PEX8603 internal registers, run internal output probe mode, monitor error counters, and monitor status of all ports. The PEX8603 RDK provides a 10 pin I2C header (JP2). The pin header included is compatible with the Aardvark I2C/SPI Host Adapter Part Number: TP240141 by TotalPhase. -
Page 18: Fatal_Err#, And Inta
2.14 Reset Circuitry The reset circuit of PEX8603 RDK contains a two input AND gate and a reset chip. The PERST# from the PCI Express male connector and the manual reset from the pushbutton switch input to the AND gate and the output of the AND gate is fed into the reset chip. -
Page 19: Port Good Indicator Leds
The port indicator LED is either on, off, or flashing to indicate the link status. These states are shown in the table below. The RDK has a total of 3 LED indicators for Port 0-2. The D6 LED is not used in the PEX8603 RDK. Figure 12 Lane Good LEDs Table 7. -
Page 20: Pcie Protocol Debug
PEX8603 TQFP-AIC RDK 2.16 PCIe Protocol Debug All PCIe Lanes pass through an Agilent soft touch midbus probe footprint in order to monitor PCIe traffic. Figure 13: Midbus 2.0 Probe Footprint 2.17 WAKE# and Vaux Support The Wake# signals will be connected together and Vaux will be routed from the upstream port to all downstream slots. -
Page 21: Rdk Configurations
3 RDK Configurations The PEX8603 RDK can be configured to operate in one of several modes as described in this section. The modes can be entered by changing jumpers and configuration modules. The configuration modules control the routing of the PCIE lanes and Refclk, and the strap pin dipswitches configure the modes of the PEX8603. -
Page 22: Hardware Strap Pins
PEX8603 TQFP-AIC RDK 3.2 Hardware Strap Pins The PEX8603 RDK has a number of strap pins which provide the capability to perform various types of hardware initialization without the use of EEPROM. Table 9 shows the port configuration strap pin values. -
Page 23: Hardware Jumpers
PEX8603 TQFP-AIC RDK 3.4 Hardware Jumpers The PEX8603 RDK has a few jumper settings for testing purposes. These can be left at their default settings, as detailed below: Table 10. PEX8603 Jumper Settings Jumper Default Setting Description Connects the EE_CS# signal of the PEX8603 to the EEPROM.Can be used to disable the EEPROM for testing.
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