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PLX Technology PCI 9056RDK-LITE Hardware Reference Manual

Rapid development kit
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PCI 9056RDK-LITE
Hardware Reference Manual

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Summary of Contents for PLX Technology PCI 9056RDK-LITE

  • Page 1 PCI 9056RDK-LITE Hardware Reference Manual...
  • Page 3 PCI 9056RDK-LITE Hardware Reference Manual Version 1.4 January 2006 Website: http://www.plxtech.com/ Technical Support: http://www.plxtech.com/support/ Phone: 408 774-9060 800 759-3735 Fax: 408 774-2169...
  • Page 4 © 2006 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
  • Page 5 BOUT ANUAL This document describes the PLX PCI 9056RDK-LITE Rapid Development Kit from a hardware perspective. It contains a description of all major functional circuit blocks on the board. This manual also includes the complete schematics and bill of materials.

  • Page 7: Table Of Contents

    32 SRAM PLXM ......12 XAMPLES OF ESTING THE OARD WITH 4. CPLD V ......................13 ERILOG 4.1 Verilog Code ..........................13 5. B ...................17 ILL OF ATERIALS CHEMATICS PCI 9056RDK-LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.
  • Page 8 Figure 2-2. BGA Device Prototyping Diagram....................9 IST OF ABLES Table 2-1. PCI 9056RDK-LITE Processor/Local Bus Memory Map............. 4 Table 2-2. Long Serial EEPROM Load Registers ..................5 Table 2-3. Extra Long Serial EEPROM Load Registers................6 Table 2-4. RS-232 Transceiver Configuration....................7 Table 2-5.

  • Page 9: General Information

    1. GENERAL INFORMATION 1.1 About the PCI 9056RDK-LITE The PCI 9056RDK-LITE (RDK-LITE) is a flexible development platform for designs using the PCI 9056 with generic 32-bit Processor/Local Bus devices. The RDK-LITE is shipped pre-configured for de- multiplexed generic address/data bus (C mode) operation, but is very easily reconfigured for multiplexed address/data bus (J mode) applications.

  • Page 10: Features

    Software Development defined status/debug LEDs Kit (SDK) documentation. • Built-in DB9 connector and programmable DTE/DCE RS-232 transceiver for adding a serial port PCI 9056RDK-LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.

  • Page 11: Hardware Architecture

    2. HARDWARE ARCHITECTURE This section provides a detailed description of the hardware included in the PCI 9056RDK-LITE. Figure 2-1 shows the RDK hardware block diagram. PCI 9056RDK-LITE Hardware Block Diagram Hardware Modules RS232 Transceiver Reset Circuit Prototyping Area & Test...

  • Page 12: System Architecture

    SRAM in Direct Slave mode. The microprocessor can also program the PCI 9056 I/O Accelerator to perform DMA data transfers between the PCI bus and the SRAM. Table 2-1. PCI 9056RDK-LITE Processor/Local Bus Memory Map Hex Address Chip Select Device...

  • Page 13: Serial Eeprom

    00C3 LBRD0[15:0] PCI-to-Local Address Space 0 and Expansion ROM 0000 MSW of Range for Direct Master-to-PCI DMRR[31:16] 0000 LSW of Range for Direct Master-to-PCI DMRR[15:0] PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.

  • Page 14: Table 2-3. Extra Long Serial Eeprom Load Registers

    Power Management Data / PMCSR Bridge Support Extensions 0000 PMDATA[7:0]/ PMCSR_BSE[7:0] (the LSB is reserved) Power Management Control/Status PMCSR[15:0] 0000 (Bits 15, 7:2, and 1:0 are reserved) PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.

  • Page 15: Synchronous Burst Sram

    Processor/Local Bus devices. The chip select signals are partially decoded from the upper four address lines (LA31-LA28) Processor/Local Bus. They programmed by altering the CPLD Verilog code. PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.

  • Page 16: Debug And Status Leds

    RDK, which can be used to install a 3.3V, 512KBx8 Flash memory device. Its power and ground are pre-wired and it has pads available board control signals data/address lines. PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.

  • Page 17: Figure 2-2. Bga Device Prototyping Diagram

    Plug Ironwood Minigrid Socket (BGA 1 or BGA 2 only) Solder 0.018" RDK PCB 0.0165" (BGA3) 0.022" (BGA1, BGA2) Figure 2-2. BGA Device Prototyping Diagram PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.

  • Page 18: Table 2-6. Thirty (30) Surface Mount Footprints

    Quantity Pin Pitch Examples of Applications BGA 1 (20x20) 1.5mm PLX PCI 9054 BGA 2 (26x26) 0.05" PMC801/821/823/850 BGA 3 (25x25) 1.0mm PPC403GC/GCX, TI 320C6202 PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.

  • Page 19: Power Supply

    R104 1/10w, 10K ohm, 5% R105 1/10w, 10K ohm, 5% R106 1/10w, 10K ohm, 5% R107 1/10w, 10K ohm, 5% R108 1/10w, 10K ohm, 5% PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.

  • Page 20: Examples Of Testing The O N Board 32K X 32 Sram With Plxm On

    Type in dl s0 to compare the data from step G. el s0+4 22222222 el s0+8 33333333 el s0+c 44444444 el s0+10 55555555 el s0+14 66666666 el s0+18 77777777 el s0+1c 88888888 PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.

  • Page 21: Cpld Verilog Code

    [3:0] sram_bwn; output [3:0] csn; [9:2] sram_adds; [1:0] lbg; sramcsn,sramoen,lholda; readyn,btermn; // internal veriables [3:0] a31_28; [1:0] state; oer,oeb; BUFE tt1(.O(readyn),.E(!oer),.I(oer)); BUFE tt2(.O(btermn),.E(!oeb),.I(oeb)); PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.
  • Page 22 <= 0; if (lwdrdn) oer <= 'b0; else oer <= 'b1; state <= s1; else begin oer <= 'b1; sramcsn <= 1; state <= s0; PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.
  • Page 23 <=1; sramcsn <=0; oer <='b0; oeb <='b1; state <=s1; else begin sram_adds[9:2] <=sram_adds[9:2]+1; sramoen <=0; sramcsn <=0; oer <='b0; oeb <='b1; state <= s2; PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.
  • Page 24 (!lhold && lbr[1]) lbg[1] <= lbr[1]; else lbg[1] <= 0; if (!lhold && !lbr[1] && lbr[0]) lbg[0] <= lbr[0]; else lbg[0] <= 0; endmodule PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.

  • Page 25: Bill Of Materials / Schematics

    5. BILL OF MATERIALS / SCHEMATICS The following pages list the bill of materials and the schematics for the PCI 9056RDK-LITE circuit board. The PCI 9056 is a 256-pin, 1.0mm pitch FPBGA package. The PCI 9056 signal names used in the schematics are the C mode signal names, except for the POM connector, which uses J mode signal names.
  • Page 26 Cap. Ceramic, 1uF, 16V, C10, C12, C34- Kemet ECJ-3YB1C05K SMT, 1206 Digi-Key Cap. Tantalum, 10uF, C1, C3, C5, C7, Panasonic ECS-T1DC106R SMT, Ccase Newark 20V, Ccase C32, C61-C64 PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.
  • Page 27 Switch, microminiature C&K 8631ZQD2 Through Hole Digi-Key pushbutton, off-Mom Micron IC, 1Mb, syncbust MT58L32L32FT-7.5 100-pin TQFP Marshall Technology SRAM, 32Kx32, 7.5ns PLX Part #: 91-0020-017-A PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.
  • Page 28 PCI 9056RDK- LITE Hardware Reference Manual v1.4 © 2006 PLX Technology, Inc. All rights reserved.
  • Page 29 Modified IDDQEN# circuit, changed R92 to 10K and pull-up to 2.5V, 5/6/2002 removed pull-down R91(10K) for LA28 PCI 9056RDK-LITE BLOCK DIAGRAM swapped source and drain of U15, removed R83 and added R86 (0 ohm) 7/3/2002 for revision BA silicon 8/12/2002 reconnected pin 6 of RN20 from 3.3V to ground for BREQo signal...
  • Page 30 0.01uF 0.01uF 0.01uF 3.3VB36 3.3VB41 3.3VB43 3.3VB54 VIOA59 0.01uF 0.01uF 0.01uF 0.01uF 0.047uF PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com Title 32-bit PCI Card Edge Connector Size Document Number Custom 91-0020-200-A Date: Friday, December 30, 2005 Sheet...
  • Page 31 0.01uF 3.3VCC LCLK LHOLD LVCC LHOLDA BREQi 3.3VCC CLK1 Ferrite 500mA BIGEND# LA28 PLX TECHNOLOGY, INC. CLK2 CLK_66MHZ 4 osc_halfsize 870 Maude Ave, Sunnyvale, CA 94085 SRAM_CLK 4 CLK3 0.1uF 10uF www.plxtech.com OSC_CLK R72- R74, and R85 should not Title...
  • Page 32 For C mode (default), install R46,R48,R50,R94 , R114 OUT23 IN23 R96,R98,R100,R102,R104,R106 and R108, OUT24 IN24 PLX TECHNOLOGY, INC. remove R47, R49 and R5,R93,R95,R97,R99, OE1# 870 Maude Ave, Sunnyvale, CA 94085 R101,R103,R105,and R107 OE2# www.plxtech.com For J mode, it is vice versa.
  • Page 33 GREEN PB41 3.3VCC GREEN PB42 GREEN RESET# PB45 PB43 RESET# RST_IN GREEN PLX TECHNOLOGY, INC. PB44 LRESET# 3.3VCC 870 Maude Ave, Sunnyvale, CA 94085 MAX6306UK30D1-T GREEN www.plxtech.com Title Install R41, remove R40, R43 PLX Option Module Connector Power On and R39 by default.
  • Page 34 PK54 PK58 D9: LD9 PK55 PK57 D10: LD10 PK56 D11: LD11 Logic Analyzer Header D12: LD12 PLX TECHNOLOGY, INC. D13: LD13 870 Maude Ave, Sunnyvale, CA 94085 D14: LD14 www.plxtech.com Title D15: LD15 Logic Analyzer Test Headers Size Document Number...
  • Page 35 PC79 PF13 PF20 PF29 PC80 PF12 PF21 PF28 PC80 PF12 PF21 PF28 PC81 PF11 PF22 PF27 PLX TECHNOLOGY, INC. PC81 PF11 PF22 PF27 PC82 PF10 PF23 PF26 PC82 PF10 PF23 PF26 PC83 PF24 PF25 870 Maude Ave, Sunnyvale, CA 94085...
  • Page 36 PG193 PG44 PG94 PG144 PG194 PG41 PG140 PG44 PG94 PG144 PG194 PG45 PG95 PG145 PG195 PG42 PG139 PLX TECHNOLOGY, INC. PG45 PG95 PG145 PG195 PG46 PG96 PG146 PG196 PG46 PG96 PG146 PG196 PG47 PG97 PG147 PG197 870 Maude Ave, Sunnyvale, CA 94085...
  • Page 37 PCB under the footprint of 240-pin PQFP (FP16). They are arranged as FP19 inside of FP20 and FP20 inside of FP18. All of them PLX TECHNOLOGY, INC. share prototyping holes with FP16. 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com...
  • Page 38 PH46 PH96 PH146 PH196 PH[1:208] PH47 PH97 PH147 PH197 PH47 PH97 PH197 PH147 PH48 PH98 PH148 PH198 PLX TECHNOLOGY, INC. PH48 PH98 PH148 PH198 PH49 PH99 PH149 PH199 PH49 PH99 PH149 PH199 PH50 PH100 PH150 PH200 Note: three footprints are placed on the component...
  • Page 39 PJ49 PJ77 VSS2 PJ115 VSS3 PJ50 VSS3 PJ116 VSSQ1 PJ51 VSSQ1 PJ117 VSSQ2 PJ52 VSSQ2 PJ118 PLX TECHNOLOGY, INC. VSSQ3 PJ53 VSSQ3 PJ119 PJ24 NC/RFU VSSQ4 PJ54 PJ78 NC/RFU VSSQ4 PJ120 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com Title 256Mb SDRAM...
  • Page 40 160-pin TQFP footprint. The 128-pin TQFP PI45 PI95 PI145 PI45 PI95 PI145 footprint is placed on the solder side directly under FP26. PI46 PI96 PI146 PLX TECHNOLOGY, INC. PI46 PI96 PI146 PI47 PI97 PI147 FP27 also shares prototyping holes with FP26 PI47 PI97 PI147...
  • Page 41 3. Data Bus Connector (LAH3) 4. Data Bus Connector (LAH4) 5. Address Bus Connector (LAH1) 6. Address Bus Connector (LAH2) 7. Marked as is prototype area PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com Title Suggested Board Layout Size...

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