ONTENTS 1. General Information ..........................1 PEX 8311 Features ......................... 2 PEX 8311RDK Features........................2 2. PEX 8311RDK System Architecture ...................... 3 3. PEX 8311RDK Hardware Architecture ....................4 PEX 8311 PCI Express Bridge Device.................... 4 Serial EEPROM ..........................4 3.2.1...
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Table 3-1. Long Serial EEPROM Load Registers ..................6 Table 3-2. Extra Long Serial EEPROM Load Registers................7 Table 3-3. PEX 8311RDK Processor/Local Bus Memory Map ..............10 Table 3-4. PEX 8311RDK LED Indicators ....................11 Table 3-5. PEX 8311RDK Power supply currents..................12 Table 3-6.
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PLX assumes no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the PEX 8311RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.
The PEX 8311RDK allows the upstream PCI Express port of the PEX 8311 device to be connected to a host system slot by way of a standard PCI Express edge connector (the PEX 8311RDK is designed to plug into a PCI Express motherboard slot).
PEX 8311 configured in Endpoint mode. This allows bridging between a PCI Express base board and local bus processors or logic. The PEX 8311RDK is designed to showcase many of the PEX 8311 features when operating in Endpoint mode.
8311 automatically determines the appropriate addressing mode. The SPI operates at up to 25 MHz and can directly interface with the PEX 8311. The Atmel AT25640 device as used in the PEX 8311RDK is recommended. Other compatible 128-byte serial EEPROM’s include the Atmel AT25010A, Catalyst CAT25C01, and ST Microelectronics M95010W.
When the PEX 8311 is operating in Root Complex mode then the internal clock must be provided from an external source. While the PEX 8311RDK is not designed to operate in Root Complex mode provision has been made for an external clock oscillator to provide the internal clock to the PEX 8311. The components for the external clock are not assembled nor do they appear on the BOM.
Land is provided for the PCI Express RefClk to be generated onboard by an optional clock synthesizer (U12), using a 25-MHz crystal for the seed frequency. The PEX 8311RDK can use the IC557G-03 part from Integrated Circuit systems, Inc., though any comparable synthesizer is sufficient. RefClk is routed to the PEX 8311.
ON, GPIO3 = Input by default PEX 8311RDK Power The PEX 8311RDK has two sources for DC power. The first source is the card edge connector (P1). This x1 connector provides up to 500 mA at +12V , and 3.0A at +3.3V .
PEX 8311 to be measured under different operating conditions. Table 3-6 details the jumper and resistor settings for the main power options. For the uncommitted FPGA power options please see section 4.4.2.4 Uncommitted FPGA power supplies. Table 3-6. PEX 8311RDK Power jumper and resistor options Jumper Factory Setting...
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7 of the schematics. To route the PCI Express clocks to the PEX 8311 remove R12 and R13 and insert R1 and R2. When operating in Endpoint mode the power for the PEX 8311RDK is normally provided by the PCI Express edge connector. If power is unavailable from this connector other means must be used to provide the +12V and +3.3V required by the board.
Figure 4-1. PEX 8311RDK Component Placement The PEX 8311RDK’s form factor is based on the PCI Express CEM specification. The board is an eight- layer 6.6"L x 8.15"W PC board. The board height is greater than that noted in the PCI Express CEM specification and care must be taken to ensure that the board will fit within the target PC.
J8 (1.5 VCC) J9 (2.5 VCC) J7 (3.3 VCC) Three 3.3 VCC test points (TP9-11), are scattered across the PEX 8311RDK to allow voltage monitoring. TP1 is connected to the PEX 8311 PWR_OK output TP2 can be used to monitor the PEX8311 internal clock External power can be monitored at the ATX connector (J4) J1 provides access to the PEX 8311 JTAG port;...
Plane capacitance filters noise above approximately 100 MHz. The footprints for the discrete decoupling capacitors are designed such that the inductance between the pad and plane is reduced by careful via placement. (Refer to Figure 4-2. PEX 8311RDK Decoupling Capacitor Footprints) PEX 8311RDK Hardware Reference Manual, Version 0.90...
4.2.3 PCB Stackup The PEX 8311RDK is an 8-layer, 60-mil thick PCB. The target signal impedance for all routing layers is 55 Ohms ±10% single-ended impedance and 100 Ohms ±5% differential. Figure 4-3 details the layers used in the PCB manufactuer. The thickness of the various layers is detailed in Table 4-2. Layer thickness.
0.60 MidBus LAI Footprints The PEX 8311RDK has one half-size MidBus LAI footprint site (J5), which can be used to probe the high- speed PCI Express serial lanes, or populated with a shroud to allow third-party PCI Express logic analyzers to view the serial data.
Bill of Materials / Schematics The following pages contain the PEX 8311RDK bill of materials and schematics. Table 9-1. PEX 8311RDK Bill Of Materials Item Package Subcon. Man's Part # Schematic Reference Subcon. Type Part # SURFACE MOUNT COMPONENTS Cap, Ceramic, 0.001...
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5,9,11 10uF 10uF 10uF 10uF 10uF 10uF 8311_1.5V PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 Place one cap. to www.plxtech.com www.plxtech.com...
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0.1uF 0.01uF 0.01uF 0.1uF 0.1uF 0.01uF 0.01uF 0.1uF 0.1uF PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. 0.01uF 0.01uF 10uF 10uF 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085...
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0.01uF 0.01uF 0.01uF For J mode, it is vice versa. LD[31:0] 3,5,6,9,10,11,12 PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com www.plxtech.com...
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LED8 R124 R124 R125 R125 1.2K 1.2K R127 R127 PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com www.plxtech.com www.plxtech.com Title...
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PLX Option Module 1 (POM1) PLX Option Module 1 (POM1) 2X50 Connector 3,4,5,9,10,11,12 LD[31:0] PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com...
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The components on this sheet are not Clock Circuit installed by default. 3.3VCC 3.3VCC 2 R136 R136 10_NP 10_NP R641 R641 0.01uF_NP 0.01uF_NP 0.01uF_NP 0.01uF_NP 10K_NP 10K_NP PLACE R137,R138,R141,R142,R143,R145,R147,R148 CLOSE TO U12 Internal pull-up resistor in OE, S0/1, SS0/1 R137 R137 33_NP 33_NP...
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The components on this sheet are not PCIE3.3VCC 2.5VCC Side D bus installed by default. R151 R151 0_NP 0_NP PCIE3.3VCC D[36:1] 12,13 R152 R152 0_NP 0_NP 2.5VCC Note this is designed for the Xilinx R153 R153 0_NP 0_NP USRVCC XCF01S or XCF02S device in their R154 R154 0_NP...
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The components on this sheet are not installed by default. Side A bus 8,13 A[36:1] 1.5VCC PCIE3.3VCC R176 R176 0_NP 0_NP 1.5VCC 2.5VCC R177 R177 0_NP 0_NP C102 C102 R178 R178 0_NP 0_NP R179 R179 0_NP 0_NP 8,13 R180 R180 56_NP 56_NP 10nF_NP...
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The components on this sheet are not installed by default. Side B bus 8,13 B[36:1] PCIE3.3VCC R273 R273 0_NP 0_NP 2.5VCC R274 R274 0_NP 0_NP C114 C114 R275 R275 0_NP 0_NP 10nF_NP 10nF_NP R276 R276 0_NP 0_NP 3,4,5 R277 R277 0_NP 0_NP R278...
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The components on this sheet are not installed by default. Side C bus 8,13 C[36:1] PCIE3.3VCC R381 R381 0_NP 0_NP 2.5VCC R382 R382 0_NP 0_NP C128 C128 USRVCC R383 R383 0_NP 0_NP 10nF_NP 10nF_NP R384 R384 0_NP 0_NP R385 R385 0_NP 0_NP VC11...
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The components on this sheet are not installed by default. Side D bus 8,13 D[36:1] PCIE3.3VCC R488 R488 0_NP 0_NP 2.5VCC R489 R489 0_NP 0_NP C141 C141 USRVCC R490 R490 0_NP 0_NP 10nF_NP 10nF_NP R491 R491 0_NP 0_NP 8,13 R493 R493 0_NP 0_NP...
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The components on this sheet are not installed by default. A[36:1] 8,10 B[36:1] 8,11 C[36:1] 8,12 D[36:1] PF19 PF19 PF37 PF37 PF55 PF55 PF73 PF73 PF91 PF91 PF109 PF109 PF127 PF127 PF20 PF20 PF38 PF38 PF56 PF56 PF74 PF74 PF92 PF92 PF110 PF110...
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PEX8311 PEX8311 Title Title Title NC BALLS NC BALLS NC BALLS Size Size Size Document Number Document Number Document Number <Doc> <Doc> <Doc> 91-0058-000-A Date: Date: Date: Wednesday, December 14, 2005 Wednesday, December 14, 2005 Wednesday, December 14, 2005 Sheet Sheet Sheet...
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