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PEX 8311RDK
Hardware Reference Manual

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Summary of Contents for PLX Technology PEX 8311RDK

  • Page 1 PEX 8311RDK Hardware Reference Manual...
  • Page 3 PEX 8311RDK Hardware Reference Manual Version 0.90 December 2005 Website: http://www.plxtech.com Support: http://www.plxtech.com/support Phone: 408 774-9060 800 759-3735 Fax: 408 774-2169...
  • Page 4 © 2005 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
  • Page 5: Table Of Contents

    ONTENTS 1. General Information ..........................1 PEX 8311 Features ......................... 2 PEX 8311RDK Features........................2 2. PEX 8311RDK System Architecture ...................... 3 3. PEX 8311RDK Hardware Architecture ....................4 PEX 8311 PCI Express Bridge Device.................... 4 Serial EEPROM ..........................4 3.2.1...
  • Page 6 Table 3-1. Long Serial EEPROM Load Registers ..................6 Table 3-2. Extra Long Serial EEPROM Load Registers................7 Table 3-3. PEX 8311RDK Processor/Local Bus Memory Map ..............10 Table 3-4. PEX 8311RDK LED Indicators ....................11 Table 3-5. PEX 8311RDK Power supply currents..................12 Table 3-6.
  • Page 7 PLX assumes no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the PEX 8311RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.
  • Page 9: General Information

    The PEX 8311RDK allows the upstream PCI Express port of the PEX 8311 device to be connected to a host system slot by way of a standard PCI Express edge connector (the PEX 8311RDK is designed to plug into a PCI Express motherboard slot).
  • Page 10: Pex 8311 Features

    Socketed oscillator for Processor/Local Bus clock and local logic PLX J-Bus Option Module (POM) connector for expansion Option for on board PCI Express reference clock generation PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 11: Pex 8311Rdk System Architecture

    PEX 8311 configured in Endpoint mode. This allows bridging between a PCI Express base board and local bus processors or logic. The PEX 8311RDK is designed to showcase many of the PEX 8311 features when operating in Endpoint mode.
  • Page 12: Pex 8311Rdk Hardware Architecture

    PEX 8311 data book. Serial EEPROM The PEX 8311 bridge device has two EEPROM’s associated with it. These EEPROM’s can be used to load configuration data on power-up. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 13: Spi Eeprom

    8311 automatically determines the appropriate addressing mode. The SPI operates at up to 25 MHz and can directly interface with the PEX 8311. The Atmel AT25640 device as used in the PEX 8311RDK is recommended. Other compatible 128-byte serial EEPROM’s include the Atmel AT25010A, Catalyst CAT25C01, and ST Microelectronics M95010W.
  • Page 14: Microwire Serial Eeprom Contents

    MSW of PCI Configuration Address Register for 0000 DMCRGA[31:16] Direct Master-to-PCI I/O Configuration LSW of PCI Configuration Address Register for 0000 DMCFGA[15:0] Direct Master-to-PCI I/O Configuration PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 15: Local And Pci Express Hardware Elements

    SBSRAM in Direct Slave mode. The host can also program the PEX 8311 to perform DMA data transfers between the PCI Express bus and the SBSRAM. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 16: Local Clock

    When the PEX 8311 is operating in Root Complex mode then the internal clock must be provided from an external source. While the PEX 8311RDK is not designed to operate in Root Complex mode provision has been made for an external clock oscillator to provide the internal clock to the PEX 8311. The components for the external clock are not assembled nor do they appear on the BOM.
  • Page 17: Plx Option Module Connector

    POM module. Schematic sheet 6 provides the connector signal details. The connector to mate to J3 can be purchased from AMP distributors the part number is: 6-104652-0 PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 18: Hardware Memory Map

    Land is provided for the PCI Express RefClk to be generated onboard by an optional clock synthesizer (U12), using a 25-MHz crystal for the seed frequency. The PEX 8311RDK can use the IC557G-03 part from Integrated Circuit systems, Inc., though any comparable synthesizer is sufficient. RefClk is routed to the PEX 8311.
  • Page 19: Reset Circuitry

    ON, GPIO3 = Input by default PEX 8311RDK Power The PEX 8311RDK has two sources for DC power. The first source is the card edge connector (P1). This x1 connector provides up to 500 mA at +12V , and 3.0A at +3.3V .
  • Page 20: Pex 8311 Power Jumpers And Resistor Options

    PEX 8311 to be measured under different operating conditions. Table 3-6 details the jumper and resistor settings for the main power options. For the uncommitted FPGA power options please see section 4.4.2.4 Uncommitted FPGA power supplies. Table 3-6. PEX 8311RDK Power jumper and resistor options Jumper Factory Setting...
  • Page 21: Power Management Signaling

    To use the clock source on the RDK remove R53 and assemble R52, R150, C96, C97 and U13. The maximum operating frequency for U13 should be 66MHz. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 22 7 of the schematics. To route the PCI Express clocks to the PEX 8311 remove R12 and R13 and insert R1 and R2. When operating in Endpoint mode the power for the PEX 8311RDK is normally provided by the PCI Express edge connector. If power is unavailable from this connector other means must be used to provide the +12V and +3.3V required by the board.
  • Page 23: Mechanical Architecture

    Figure 4-1. PEX 8311RDK Component Placement The PEX 8311RDK’s form factor is based on the PCI Express CEM specification. The board is an eight- layer 6.6"L x 8.15"W PC board. The board height is greater than that noted in the PCI Express CEM specification and care must be taken to ensure that the board will fit within the target PC.
  • Page 24: Monitoring Points, Test Headers, Indicators, Control, And Dip Switch Summary

    J8 (1.5 VCC) J9 (2.5 VCC) J7 (3.3 VCC) Three 3.3 VCC test points (TP9-11), are scattered across the PEX 8311RDK to allow voltage monitoring. TP1 is connected to the PEX 8311 PWR_OK output TP2 can be used to monitor the PEX8311 internal clock External power can be monitored at the ATX connector (J4) J1 provides access to the PEX 8311 JTAG port;...
  • Page 25: Indicators

    Plane capacitance filters noise above approximately 100 MHz. The footprints for the discrete decoupling capacitors are designed such that the inductance between the pad and plane is reduced by careful via placement. (Refer to Figure 4-2. PEX 8311RDK Decoupling Capacitor Footprints) PEX 8311RDK Hardware Reference Manual, Version 0.90...
  • Page 26: Pcb Stackup

    4.2.3 PCB Stackup The PEX 8311RDK is an 8-layer, 60-mil thick PCB. The target signal impedance for all routing layers is 55 Ohms ±10% single-ended impedance and 100 Ohms ±5% differential. Figure 4-3 details the layers used in the PCB manufactuer. The thickness of the various layers is detailed in Table 4-2. Layer thickness.
  • Page 27: Midbus Lai Footprints

    0.60 MidBus LAI Footprints The PEX 8311RDK has one half-size MidBus LAI footprint site (J5), which can be used to probe the high- speed PCI Express serial lanes, or populated with a shroud to allow third-party PCI Express logic analyzers to view the serial data.
  • Page 28: Uncommitted Fpga Footprint

    Any combination of the above can be used. Table 4-4 shows the resistor options used to connect the Altera Cyclone or the Xilinx Spartan-3E arrays to the PEX 8311 local bus. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 29: Table 4-4. Uncommitted Fpga Resistor Configuration

    43 I/O LA9_X 44 I/O 3.3V LA10_X B8 45 1.2V 46 GND 1.5V 47 IP LA16 48 IP LA17 49 3.3V LA8_A 50 I/O LD15 PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 30 PMEIN#_X 94 I/O BTERM# 95 IP F_TDI User IP 96 I/O CCS# 97 I/O DMPAF/EOT C25 98 I/O DREQ0# 99 GND LA13_A 100 3.3V LA14_A PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 31 The value required will depend on the loading but will typically be in the range of 30 to 100 ohms. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 32: Programming The Uncommitted Fpga

    Depending on the programmer used pins 4 and 10 of JP6 may need to be pulled to the appropriate voltage, see notes 1 and 2 below and the appropriate Altera documentation. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 33: Table 4-5. Altera Uncommitted Fpga Jtag Interconnections

    7) DCLK is connected to GPIO1. When JP3 is in position 2-3 GPIO1 is strapped to GND and must always be configured as an input. In addition to the above resistors the appropriate power supply and ground resistors must also be populated. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 34: Table 4-6. Xilinx Uncommitted Fpga Jtag Interconnections

    5) If this pin is connected to LA19 through R283 then R284 and R367 are not required as this pin is pulled high using RN11. In addition to the above resistors the appropriate power supply and ground resistors must also be populated. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 35: 4.4.2.3.2 Programming The Fpga Through The Gpio

    2.5V supply for the FPGA was sourced from the USRVCC – see the Xilinx application notes for further details regarding reverse currents. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 36: Programming The Uncommitted Fpga From The Configuration Prom

    2.5V supply for the FPGA was sourced from the USRVCC – see the Xilinx application notes for further details regarding reverse currents. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 37: Uncommitted Fpga Power Supplies

    Although the schematics show U14 to be a 2.5V regulator any comparable regulator which can fit the SOT-223 layout can be used. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 38: Uncommitted Fpga Pull-Ups/Downs

    FPGA the upper portion of the LA bus can be left unconnected releasing FPGA I/O. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 39: Rdk Mode Configuration

    1/10w, 0 ohm, 5% R110 R111 1/10w, 0 ohm, 5% R112 1/10w, 0 ohm, 5% R113 1/10w, 0 ohm, 5% LA29/ALE 1/10w, 10K, 5% 1/10w, 4.7K ohm, 5% PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 41: Examples Of Testing The Onboard 32Kx32 Sbsram With Plxmon

    HBuf 99999999 el HBuf+4 88888888 el HBuf+8 77777777 el HBuf+c 66666666 el HBuf+10 55555555 el HBuf+14 44444444 el HBuf +18 33333333 el HBuf+1c 22222222 PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 42 Descriptor Pointer (90h) value from 8 to 0. Click the [Start Transfer] button to perform a DMA transfer again Type in dl s0 to compare the data from step G. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 43: Cpld Verilog Code

    // chip select signals for the board. They are CS[3:0] with addresses csn_0: 1000_0000h csn_1: 2000_0000h csn_2: 3000_0000h csn_3: 4000_0000h wire [3:0] csn = (adds_4msb == 4'b0001) ? 4'b1110: (adds_4msb == 4'b0010) ? 4'b1101: PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 44 (lwdrdn && (!blastn)) begin sram_adds[9:2] <=sram_adds[9:2]+1; sramoen <=1; sramcsn <=1; oer <='b1; oeb <='b1; state <= s0; else if (lwdrdn && blastn) begin if (sram_adds[9:2]== 'hfe) PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 45 <='b0; sram_adds[9:2] <= sram_adds[9:2]+1; state <=s3; else begin sram_adds[9:2] <= sram_adds[9:2]+1; sramoen <=0; sramcsn <=0; oer <='b0; oeb <='b1; state <=s2; s3: begin PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 46 (!lhold && lbr[1]) lbg[1] <= lbr[1]; else lbg[1] <= 0; if (!lhold && !lbr[1] && lbr[0]) lbg[0] <= lbr[0]; else lbg[0] <= 0; endmodule PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 47: References

    5440 SW Westgate Drive #217 Portland, OR 97221 USA Tel: 503-291-2569 Fax: 503-297-1090 http://www.pcisig.com PCI Express Card Electromechanical (CEM) Specification, Revision 1.0a PCI Express-to-PCI Bridge Specification 1.0 PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 49: Bill Of Materials / Schematics

    Bill of Materials / Schematics The following pages contain the PEX 8311RDK bill of materials and schematics. Table 9-1. PEX 8311RDK Bill Of Materials Item Package Subcon. Man's Part # Schematic Reference Subcon. Type Part # SURFACE MOUNT COMPONENTS Cap, Ceramic, 0.001...
  • Page 50 IC, Serial Atmel AT25640A-10PI-2.7 EEPROM, SPI, 64K, DIP, 8-pin AT25640 IC, Serial Atmel AT93C56A-10PU-2.7 EEPROM, 3-wire, DIP, 8-pin AT93C56/66A PCI Bracket, Keystone 9203 BRACKET1 Blank PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 51 NOTE: NOT POPULATED NO VALUE COMPONENTS FROM SHEETS 8 TO 12 OF THE SCHEMATICS ARE NOT LISTED. SEE SECTION 4.4.2 FOR COMPONENT VALUES NOTE: OTHER NOT POPULATED COMPONENTS ARE NOT LISTED AT THIS TIME Customer Name: PLX PLX Part #: 91-0058-000-A Product Name: PEX 8311RDK PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.
  • Page 52 This schematic includes minor board errata's which are not implemented in the PCB layout. See PEX8311RDK Errata Rev. 1.0, Dec. 2005 for details. © 2005 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata.
  • Page 53 5,9,11 10uF 10uF 10uF 10uF 10uF 10uF 8311_1.5V PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 Place one cap. to www.plxtech.com www.plxtech.com...
  • Page 54 0.1uF 0.01uF 0.01uF 0.1uF 0.1uF 0.01uF 0.01uF 0.1uF 0.1uF PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. 0.01uF 0.01uF 10uF 10uF 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085...
  • Page 55 0.01uF 0.01uF 0.01uF For J mode, it is vice versa. LD[31:0] 3,5,6,9,10,11,12 PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com www.plxtech.com...
  • Page 56 LED8 R124 R124 R125 R125 1.2K 1.2K R127 R127 PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com www.plxtech.com www.plxtech.com Title...
  • Page 57 PLX Option Module 1 (POM1) PLX Option Module 1 (POM1) 2X50 Connector 3,4,5,9,10,11,12 LD[31:0] PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com...
  • Page 58 The components on this sheet are not Clock Circuit installed by default. 3.3VCC 3.3VCC 2 R136 R136 10_NP 10_NP R641 R641 0.01uF_NP 0.01uF_NP 0.01uF_NP 0.01uF_NP 10K_NP 10K_NP PLACE R137,R138,R141,R142,R143,R145,R147,R148 CLOSE TO U12 Internal pull-up resistor in OE, S0/1, SS0/1 R137 R137 33_NP 33_NP...
  • Page 59 The components on this sheet are not PCIE3.3VCC 2.5VCC Side D bus installed by default. R151 R151 0_NP 0_NP PCIE3.3VCC D[36:1] 12,13 R152 R152 0_NP 0_NP 2.5VCC Note this is designed for the Xilinx R153 R153 0_NP 0_NP USRVCC XCF01S or XCF02S device in their R154 R154 0_NP...
  • Page 60 The components on this sheet are not installed by default. Side A bus 8,13 A[36:1] 1.5VCC PCIE3.3VCC R176 R176 0_NP 0_NP 1.5VCC 2.5VCC R177 R177 0_NP 0_NP C102 C102 R178 R178 0_NP 0_NP R179 R179 0_NP 0_NP 8,13 R180 R180 56_NP 56_NP 10nF_NP...
  • Page 61 The components on this sheet are not installed by default. Side B bus 8,13 B[36:1] PCIE3.3VCC R273 R273 0_NP 0_NP 2.5VCC R274 R274 0_NP 0_NP C114 C114 R275 R275 0_NP 0_NP 10nF_NP 10nF_NP R276 R276 0_NP 0_NP 3,4,5 R277 R277 0_NP 0_NP R278...
  • Page 62 The components on this sheet are not installed by default. Side C bus 8,13 C[36:1] PCIE3.3VCC R381 R381 0_NP 0_NP 2.5VCC R382 R382 0_NP 0_NP C128 C128 USRVCC R383 R383 0_NP 0_NP 10nF_NP 10nF_NP R384 R384 0_NP 0_NP R385 R385 0_NP 0_NP VC11...
  • Page 63 The components on this sheet are not installed by default. Side D bus 8,13 D[36:1] PCIE3.3VCC R488 R488 0_NP 0_NP 2.5VCC R489 R489 0_NP 0_NP C141 C141 USRVCC R490 R490 0_NP 0_NP 10nF_NP 10nF_NP R491 R491 0_NP 0_NP 8,13 R493 R493 0_NP 0_NP...
  • Page 64 The components on this sheet are not installed by default. A[36:1] 8,10 B[36:1] 8,11 C[36:1] 8,12 D[36:1] PF19 PF19 PF37 PF37 PF55 PF55 PF73 PF73 PF91 PF91 PF109 PF109 PF127 PF127 PF20 PF20 PF38 PF38 PF56 PF56 PF74 PF74 PF92 PF92 PF110 PF110...
  • Page 65 PF33 PF60 PF145 PF145 PF151 PF151 PF34 PF59 PF146 PF146 PF152 PF152 PF35 PF58 PF147 PF147 PF153 PF153 PF36 PF57 PF148 PF148 PF154 PF154 PF37 PF56 PF149 PF149 PF155 PF155 PF38 PF55 PF150 PF150 PF156 PF156 PF39 PF54 PF157 PF157 PF158 PF158 PF40...
  • Page 66 PEX8311 PEX8311 Title Title Title NC BALLS NC BALLS NC BALLS Size Size Size Document Number Document Number Document Number <Doc> <Doc> <Doc> 91-0058-000-A Date: Date: Date: Wednesday, December 14, 2005 Wednesday, December 14, 2005 Wednesday, December 14, 2005 Sheet Sheet Sheet...

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