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1MRK 506 377-UEN Rev. L
10.3.2.5
Verifying the directional sensitive protection
1.
Use settings for the installation.
2.
Inject currents corresponding to the transformer rated current on both sides so that the
differential current is 0% and the bias current is 100%.
3.
Make sure that both currents are above 10 percent of the rated current values.
4.
Slowly decrease the phase angle between the sides from 180 degrees apart until TRDRSEN is
set, and note the value.
5.
Ensure that START is not set, otherwise it will block TRDRSEN.
6.
Increase the phase angle back slowly until TRDRSEN resets, and note the value.
10.3.2.6
Verifying the differential alarm
1.
Use settings for the installation.
2.
Inject currents corresponding to the transformer rated current on both sides so that the
differential current is 0% and the bias current is 100%.
3.
Decrease the injected current on one side until IDALARM is set, and note the value and alarm
delay.
4.
Increase the injected current until IDALARM resets, and note the value.
10.3.2.7
Verifying the blocking functionality
1.
Use the settings for the installation.
2.
Inject currents corresponding to the transformer rated current on both sides so that the
differential current is 0% and the bias current is 100%.
3.
Decrease the injected current on one side until TRRES is set.
4.
Increase the 2nd harmonic on one side above I2/I1Ratio and verify that TRRES is reset
(blocked).
5.
If required, use the same procedure to test the 5
10.3.2.8
Completing the test
Continue to test another function or end the test by changing the TestMode setting to Off. Restore
connections and settings to their original values if they were changed for testing purposes.
10.4
Impedance protection
10.4.1
Automatic switch onto fault logic ZCVPSOF
Prepare the IED for verification of settings outlined in Section
The automatic switch onto fault logic function ZCVPSOF is checked using secondary injection tests.
ZCVPSOF is activated either by the external input BC or by the internal DLD. FUFSPVC is done with
a pre-fault condition where the phase voltages and currents are at zero. A reverse two-phase fault
with zero impedance and a two-phase fault with an impedance corresponding to the whole line is
applied. This fault shall cause an instantaneous trip and result in a TRIP indication.
Railway application RER670
Commissioning manual
© 2017 - 2022 Hitachi Energy. All rights reserved
Testing functionality by secondary injection
GUID-98EE9BC4-BF63-42B1-A132-AFB24CA200DB v2
GUID-81496723-AF55-41A1-9EDB-711E28D3DBAC v2
GUID-B7A67797-F6BE-45CB-8502-A4C26119430A v2
th
harmonic blocking feature.
GUID-FBE8F3A7-2ADE-4C60-9590-FC4B34D8AC56 v1
"Preparing the IED to verify
Section 10
SEMOD53525-1 v2
M13850-2 v9
settings".
71
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