Linear Technology DC2491A Demo Manual page 4

DEMO MANUAL DC2491A
PCB LAYOUT
Best AC Performance: PCB Layout for Output
Capacitor C2
For ultrahigh PSRR performance, the LT3045 bandwidth
is made quite high (~1MHz), making it very close to the
output capacitor's self-resonance frequency (~1.6MHz).
Therefore, it is very important to avoid adding extra imped-
ance (ESL and ESR) outside the feedback loop. To that end,
minimize the effects of PCB trace and solder inductance
by Kelvin connecting OUTS and SET pin capacitor (C
GND directly to output capacitor (C2) terminals using split
capacitor techniques. Pad 4 connects to the OUTS pin and
Pad 1 connects to the GND side of the SET pin capacitor.
With only small AC current flowing through these connec-
tions, the impact of solder joint/PCB trace inductance on
stability is eliminated. While the LT3045 is robust enough
not to oscillate if the recommended layout is not followed,
phase/gain margin and PSRR will degrade.
4
)
SET
Figure 5. Split Pads for C2 on Top Layer of DC2491A
IN
V
IN
100 A
C1
EN/UV
PGFB
PG
SET
R
SET
Figure 4. C2 and C Connections for Best Performance
SET
LT3045
V
OUT
OUT
C
2
OUTS
4 3
GND ILIM
1 2
C
SET
dc2491af