Motorola M68MPB16Y1 User Manual page 37

Table 4-8. Logic Analyzer Connector J14 Pin Assignments (continued)
Pin
9 – 15
16 – 19
20
Table 4-9. Logic Analyzer Connector J15 Pin Assignments
Pin
1 – 3
4 – 13
14
15
16
17
18, 19
20
M68MPB16Y1UM/D
Mnemonic
IRQ1 – IRQ7 TARGET INTERRUPT REQUEST 1 - 7 – Active-low
input signals from the target that asynchronously
provides an interrupt priority level to the CPU. IRQ1
has the lowest priority, IRQ7 has the highest.
PF1 – PF7 PORT F (bits 1 - 7) – General purpose input/output
lines.
SPARE No connection
GND GROUND
Mnemonic
SPARE No connection
GND GROUND
PCLK AUXILIARY TIMER CLOCK INPUT – External input
clock source for the GPT.
PWMB PULSE WIDTH MODULATION B – Repetitive output
signals whose high time to low time ratio can be
controlled by the CPU.
PWMA PULSE WIDTH MODULATION A – Repetitive output
signals whose high time to low time ratio can be
controlled by the CPU.
PAI PULSE ACCUMULATOR INPUT – Input signal that
increments an 8-bit counter.
SPARE No connection
GND GROUND
MEVB SUPPORT INFORMATION
Signal
Signal
4-9