Page 1 MU196020A PAM4 PPG MU196040A PAM4 ED MU196040B PAM4 ED MU196060A 32G baud NRZ/PAM4 Re-Driver Operation Manual 16th Edition ● For safety and warning information, please read this manual before attempting to use the equipment. ● Additional safety and warning information is provided within the MP1900A Signal Quality Analyzer-R Operation Manual.
Page 2 Ensure that you clearly understand the meanings of the symbols BEFORE using the equipment. Some or all of the following symbols may be used on all Anritsu equipment. In addition, there may be other labels attached to products that are not shown in the diagrams in this manual.
Page 3 In addition, this warranty is valid only for the original equipment purchaser. It is not transferable if the equipment is resold. Anritsu Corporation shall assume no liability for damage or financial loss of the customer due to the use of or a failure to use this equipment, unless the damage or loss is caused due to Anritsu Corporation’s intentional or gross...
Page 4 Service and Sales office. Contact information can be found on the last page of the printed version of this manual, and is available in a separate file on the PDF version. Also, the Anritsu website provides you with contact information and a contact form.
Page 5 Before re-exporting the product or manuals, please contact us to confirm whether they are export-controlled items or not. For more details, visit https://www.anritsu.com/support/export-procedures. When you dispose of the products or manuals subject to export control, they must be physically destroyed or shredded so as not to be...
Page 6 2012/19/EU (the “WEEE Directive”) in European Union. For Products placed on the EU market after August 13, 2005, please contact your local Anritsu representative at the end of the product's useful life to arrange disposal in accordance with your initial contract and the local law.
Page 7 Anritsu electronic equipment, etc.). By using this Software, you shall be deemed to have agreed to be bound by the terms of this EULA, and Anritsu Corporation (hereafter Anritsu) hereby grants you the right to use this Software with the Anritsu specified equipment (hereafter Equipment) for the purposes set out in this EULA.
Page 8 Software with members of such organization. except as authorized by the laws and 2. You and Anritsu may terminate this EULA regulations of Japan and the United States, by a written notice to the other party 30 etc.
Page 9 CE Conformity Marking Anritsu affixes the CE conformity marking on the following products in accordance with the Decision 768/2008/EC to indicate that they conform to the EMC, LVD and RoHS directive of the European Union (EU). CE marking 1. Product Model...
Page 10 UKCA Marking Anritsu affixes the UKCA marking on the following products in accordance with the guidance to indicate that they conform to the EMC, LVD, and RoHS regulations in the United Kingdom. UKCA marking 1. Product Model Plug-in Units: MU196020A PAM4 PPG MU196040B PAM4 ED 2.
Page 11 RCM Conformity Marking Anritsu affixes the RCM mark on the following products in accordance with the regulation to indicate that they conform to the EMC framework of Australia/New Zealand. RCM marking 1. Product Model Plug-in Units: MU196020A PAM4 PPG MU196040A PAM4 ED MU196040B PAM4 ED 2.
Page 13: About This Manual
MP1900A. MU196020A PAM4 PPG MU196040A PAM4 ED MU196040B PAM4 ED MU196060A 32G baud NRZ/PAM4 Re-Driver Operation Manual Describes the panel details, performance test, maintenance, and troubleshooting of the MU196020A, MU196040A, MU196040B, and MU196060A.
Page 14 Configuration of Signal Quality Analyzer-R Series Operation Manuals (Cont’d) indicates this document. MX190000A Signal Quality Analyzer-R Control Software Operation Manual Describes the operation of the software that controls the Signal Quality Analyzer-R Series. Extended Application Operation Manual Describes the operation of the extended application for the Signal Quality Analyzer-R Series.
Page 15: Table Of Contents
Table of Contents About This Manual ..........I Chapter 1 Overview ..........1-1 Product Overview............1-2 Product Configuration ..........1-5 Specifications............1-13 Chapter 2 Before Use ......... 2-1 Installation to MP1900A ..........2-2 How to Operate Application ......... 2-2 Preventing Damage ............ 2-3 Chapter 3 Panel Layout and Connectors..
Page 16 Chapter 7 Troubleshooting ....... 7-1 Problems That Occur When Replacing Modules ..7-2 Problems That Occur During Output Waveform Observation ..............7-3 Problems That Occur During Error Rate Measurement .............. 7-4 Synchronization Failures ..........7-5 Appendix A Pseudo-Random Pattern ..... A-1 Appendix B List of Default Settings ....
Page 17 This chapter describes the overview of the following modules. ● MU196020A PAM4 PPG (hereafter, MU196020A) ● MU196040A PAM4 ED (hereafter, MU196040A) ● MU196040B PAM4 ED (hereafter, MU196040B) ● MU196060A 32G baud NRZ/PAM4 Re-Driver (hereafter, MU196060A) Product Overview ............1-2 Product Configuration ........... 1-5 1.2.1 Standard configuration ........
Page 18: Chapter 1 Overview
Chapter 1 Overview 1.1 Product Overview The MU196020A, MU196040A, MU196040B, and MU196060A, (hereinafter “MP1900A modules”) are plug-in modules that can be built into the MP1900A Signal Quality Analyzer-R. MP1900A supports error measurement with PRBS patterns, DATA patterns and various PAM4 test patterns at the following bit rates or baud rates: •...
Page 19 Product Overview MU196040A features • Supporting symbol measurement of one channel of PAM4 signal at up to 32.1 Gbaud using the built-in PAM4 Decoder circuit. • Capable of measuring signals of PRBS pattern, DATA pattern and various PAM4 patterns. • Long user-programmable patterns (256 Mbits, 256 Msymbol) •...
Page 20 • Capable of measuring flit errors and FEC symbol errors in PCIe6 FEC patterns by installing the MU196040B-w43. MU196060A features • Compensating for 32G baud NRZ/PAM4 loss by equipping with an equalizer (CTLE) circuit. Supporting PCIe5/6 CEM return path loss compensation by combining with the MU196040B.
Page 21: Product Configuration
Product Configuration 1.2 Product Configuration 1.2.1 Standard configuration Table 1.2.1-1 and Table 1.2.1-2 below show the standard configurations of the three MP1900A modules respectively. Table 1.2.1-1 Standard Configuration of MU196020A Item Model Name Product Name Q'ty Remarks Mainframe MU196020A PAM4 PPG Accessories J1632A Terminator...
Page 22 Aux Output × 2 J1717A Coaxial Adaptor (SMA-P, SMA-J) Aux Output × 2, AUX Input J1888A Precision Fixed Attenuator Data Input × 2 Table 1.2.1-4 Standard Configuration of MU196060A Item Model Name Product Name Q'ty Remarks Mainframe MU196060A 32G baud NRZ/PAM4 Re-Driver...
Page 23: Options
This value is recognized by the MP1900A. Anritsu management number. This value is not recognized by the mainframe. 0: Factory-installed option 1: Retrofit option. (Must be returned to Anritsu (Japan) when installing.) 2: Retrofit option. (Must be returned to Anritsu Service and Sales office when installing.) 3: Software option.
Page 24 Chapter 1 Overview Table 1.2.2-1 Options of MU196020A Model Name Product Name Remarks MU196020A-001 32G baud MU196020A-002 58G baud MU196020A-003 64G baud MU196020A-y12 32G to 58G baud Extension Retrofit MU196020A-y13 32G to 64G baud Extension Retrofit MU196020A-y23 58G to 64G baud Extension Retrofit MU196020A-x11 4Tap Emphasis MU196020A-x30...
Page 25 Product Configuration Table 1.2.2-2 Options of MU196040A Model Name Product Name Remarks MU196040A-001 32.1G baud Decoder MU196040A-x22 25.5G to 32.1G baud Clock Recovery MU196040A-x41 SER Measurement *1: Factory-installed hardware option *2: x = 0, 1, or 2 *3: Hardware option *4: Software option Table 1.2.2-3 Options of MU196040B Model Name...
Page 26 Chapter 1 Overview Table 1.2.2-4 Options of MU196060A Model Name Product Name Remarks MU196060A-x01 Clock Recovery for SSC *1: w = 0 or 3 *2: Software option 1-10...
Page 27: Optional Accessories
Product Configuration 1.2.3 Optional accessories Table 1.2.3-1 shows the optional accessories for the MP1900A modules. All optional accessories are sold separately. Table 1.2.3-1 Optional Accessories Model Product Name Remarks Name 34VFK50A Precision Adapter Conversion connector (V-F K-M) 34VKF50A Precision Adapter Conversion connector (V-M K-F) 41KC-3 Precision Fixed Attenuator 3 dB...
Page 28 V connector J1800A ISI Board V V connector J1917A Coaxial Semi-rigid Cable For connection between MU196040B Ext Clock In and MU196060A Clock Output Coaxial Skew Matched Cable Pair (0.8m, V J1932A Connector) K240C Precision Power Divider K connector J1889A Terminator...
Page 29: Specifications
Specifications 1.3 Specifications 1.3.1 Specifications for MU196020A Table 1.3.1-1 Operating Baud/Bit Rate Item Specifications Operating Baud/Bit Rate When the Option 001 is installed. PAM4: 2.4 to 32.1 Gbaud NRZ: 2.4 to 32.1 Gbit/s When the Option 002 or y12 is installed. PAM4: 2.4 to 58.2 Gbaud* NRZ: 2.4 to 58.2 Gbit/s* When the Option 003, y13, or y23 is installed.
Page 30 Chapter 1 Overview Table 1.3.1-1 Operating Baud/Bit Rate (Cont'd) Item Specifications When linking with MU181500B and using external clock Clock Output Rate Full Relationship Rate Input Clock Between Baud Baud Rate Setting Range Frequency Rate and Input Clock Frequency 2.4 to 15.0 Gbaud* 2.4 to 15.0 GHz 1/1 Clock Input 15.0 to 30.0 Gbaud* 7.5 to 15.0 GHz 1/2 Clock Input...
Page 31 Specifications Table 1.3.1-1 Operating Baud/Bit Rate (Cont'd) Item Specifications External Clock Clock Output Rate Full Relationship Rate Input Clock Between Baud Baud Rate Setting Range Frequency Rate and Input Clock Frequency 2.4 to 16.05 Gbaud* 2.4 to 16.05 GHz 1/1 Clock Input 16.05 to 32.1 Gbaud* 8.025 to 16.05 GHz 1/2 Clock Input 25.0 to 32.1 Gbaud*...
Page 32 Chapter 1 Overview Table 1.3.1-2 Jitter Setting Range Item Specifications* SJ1 Setting Range When SJ2 switch is the built-in SJ2, the settable Jitter Amplitude is halved. SJ1 Clock Output Rate 30 < Baud rate ≤ 32.1 Gbaud, 15 < Baud rate ≤ 17 Gbaud At Full Rate 10000 1000...
Page 33 Specifications Table 1.3.1-2 Jitter Setting Range (Cont’d) Item Specifications* SJ1 Clock Output Rate 8.5 < Baud rate ≤ 15 Gbaud At Full Rate (Cont'd) 10000 1000 100k 10M 100M 1000M Modulation Frequency [Hz] Modulation Frequency (Hz) Jitter Amplitude (UIp-p) 10 to 100k 0 to 1000 100.1k to 1M 0 to 100...
Page 34 Chapter 1 Overview Table 1.3.1-2 Jitter Setting Range (Cont’d) Item Specifications* SJ1 Clock Output Rate 2.4 ≤ Baud rate ≤ 4 Gbaud At Full Rate (Cont'd) 10000 1000 100k 100M 1000M Modulation Frequency [Hz] Modulation Frequency (Hz) Jitter Amplitude (UIp-p) 10 to 100k 0 to 500 100.1k to 1M...
Page 35 Specifications Table 1.3.1-2 Jitter Setting Range (Cont’d) Item Specifications* SJ1 Clock Output Rate 60 < Baud rate ≤ 64.2 Gbaud, At Half Rate, Quarter 30 < Baud rate ≤ 34 Gbaud, Rate 8 < Baud rate ≤ 17 Gbaud 10000 1000 100k 100M 1000M...
Page 36 Chapter 1 Overview • Relationship between Baud Rate and Input Clock Frequency is set to 1/8 Clock Input with Clock Output Rate Half Rate and Quarter Rate in Table 1.3.1-1. Table 1.3.1-2 Jitter Setting Range (Cont’d) Item Specifications* SJ1 Clock Output Rate 2.4 <...
Page 37 Specifications Table 1.3.1-2 Jitter Setting Range (Cont’d) Item Specifications* The SJ2 via MU181000 Clock and the Built-in SJ2 can be set SJ2 Setting Range exclusively. SJ2 via MU181000 15.000 001 ≤ Baud rate ≤ 32.1 Gbaud Clock Output Rate At Full Rate 100k 100M 1000M Modulation Frequency [Hz]...
Page 38 Chapter 1 Overview Table 1.3.1-2 Jitter Setting Range (Cont’d) Item Specifications* SJ2 via MU181000 3.200 001 ≤ Baud rate ≤ 6.25 Gbaud Clock Output Rate At Full Rate (Cont'd) 100k 100M 1000M Modulation Frequency [Hz] Modulation Frequency (Hz) Jitter Amplitude (UIp-p) 10 to 1M 0 to 20 1.001M to 10M...
Page 39 Specifications Table 1.3.1-2 Jitter Setting Range (Cont’d) Item Specifications* SJ2 via MU181000 60.000 001 ≤ Baud rate ≤ 64.2 Gbaud Clock Output Rate At Half Rate, Quarter Rate 100k 100M 1000M Modulation Frequency [Hz] Modulation Frequency (Hz) Jitter Amplitude (UIp-p) 10 to 1M 0 to 50 1.001M to 10M...
Page 40 Chapter 1 Overview Table 1.3.1-2 Jitter Setting Range (Cont’d) Item Specifications* SJ2 via MU181000 12.800001 ≤ Baud rate ≤ 30.0 Gbaud Clock Output Rate At Half Rate, Quarter Rate (Cont'd) 100k 100M 1000M Modulation Frequency [Hz] Modulation Frequency (Hz) Jitter Amplitude (UIp-p) 10 to 1M 0 to 50 1.001M to 10M...
Page 41 Specifications Table 1.3.1-2 Jitter Setting Range (Cont’d) Item Specifications* SJ2 via MU181000 3.600001 ≤ Baud rate ≤ 6.25 Gbaud Clock Output Rate At Half Rate, Quarter Rate (Cont'd) 100k 100M 1000M Modulation Frequency [Hz] Modulation Frequency (Hz) Jitter Amplitude (UIp-p) 10 to 1M 0 to 25 1.001M to 10M...
Page 42 Chapter 1 Overview Table 1.3.1-2 Jitter Setting Range (Cont’d) Item Specifications* SJ2 via MU181000 2.4 ≤ Baud rate ≤ 3.125 Gbaud Clock Output Rate At Half Rate, Quarter Rate (Cont'd) 100k 100M 1000M Modulation Frequency [Hz] Modulation Frequency (Hz) Jitter Amplitude (UIp-p) 10 to 1M 0 to 12.4 1.001M to 10M...
Page 43 Specifications Table 1.3.1-2 Jitter Setting Range (Cont’d) Item Specifications* Built-in SJ2 Clock 15 < Baud rate ≤ 32.1 Gbaud Output Rate Modulation Frequency (Hz) Jitter Amplitude (UIp-p) At Full Rate 0 to 1000 0 to 0.5 100M 0 to 0.5 210M 0 to 0.2 4 <...
Page 44 Chapter 1 Overview Table 1.3.1-3 External Clock Input Item Specifications Number of Inputs 1 (Single-Ended) Input frequency range 1.2 to 16.05 GHz Input amplitude 0.3 to 1.0 Vp-p (–6.5 to +4.0 dBm) Termination 50 Ω, AC Coupling Connector SMA connector (f.) Table 1.3.1-4 Aux Input Item Specifications...
Page 45 Specifications Table 1.3.1-6 Gating Output Item Specifications Number of Outputs 1 (Single-Ended) Output control ON/OFF switching Variation Burst, Repeat Burst Burst Output Burst Trigger Delay 0 to (Burst Cycle – 256) bits, 8 bits step Enable Pulse Width 16 to (Burst Cycle – 256) bits, 8 bits step Output Level 0/–1 V (H: –0.25 to 0.05 V, L: –1.25 to –0.8 V)* Repeat...
Page 46 Chapter 1 Overview Table 1.3.1-7 Generated Pattern (Cont’d) Item Specifications Zero-Substitution This is available in NRZ mode only. Additional bit 0 bit, 1 bit Pattern Length (n = 7, 9, 10, 11, 15, 20, 23) –1 (n = 7, 9, 10, 11, 15, 20, 23) Start position Bit after the longest run of zero bits Length of Consecutive...
Page 47 Specifications Table 1.3.1-7 Generated Pattern (Cont’d) Item Specifications NRZ Standard Pattern Standard-compliant NRZ-mode pattern SSPR RS-FEC When the Option z42 is installed. RS-FEC Scrambled Idle 25G 1Lane, RS-FEC Scrambled Idle 50G 2Lanes RS(544,514), RS-FEC Scrambled Idle 100G 4Lanes, RS-FEC Scrambled Idle 100G 4Lanes RS(544,514) PCIe CP in 8b/10b Encoding for PCIe1 MCP in 8b/10b Encoding for PCIe1...
Page 48 Chapter 1 Overview Table 1.3.1-8 Pattern Sequence Item Specifications Sequence Repeat, Burst Repeat Continuous Pattern Burst This is available only when Coding is NRZ. Source Internal, External-Trigger (Aux Input), External-Enable (Aux Input) Data Sequence Restart, Consecutive, Continuous Enable period Internal: 12 800 to 2 147 483 136 bits, 256 bits step External-Trigger, External-Enable: 12 800 to 2 147 483 648 bits, 256 bits step...
Page 49 Specifications Table 1.3.1-10 Error Addition (Cont’d) Item Specifications RS-FEC Symbol Error This is available whether Coding is NRZ or PAM4.* When Coding is PAM4, an error is inserted to make the PAM4 signal change by one level only. NRZ: An error is inserted every 10 bits. PAM4: An error is inserted every 10 or 20 PAM4 symbols.
Page 50 Chapter 1 Overview Table 1.3.1-10 Error Addition (Cont’d) Item Specifications RS-FEC Symbol Error (Cont’d) Error Addition Method Type1: Level 0 Level 1, Level 1 Level 2, Level 2 Level 3, Level 3 Level 2 Type2: Level 0 Level 1, Level 1 Level 2, Level 2 Level 1, Level 3...
Page 51 Specifications Table 1.3.1-10 Error Addition (Cont’d) Item Specifications Error on MSB Adds the specified symbol error. This is available only when Coding is PAM4. The set error is added to MSB only. Source Internal, External-Trigger (Rise edge trigger), External-Disable (L: Disable) Error Variation Repeat, Single (Cannot be selected when Source is External-Trigger.) Symbol Error Rate...
Page 52 Chapter 1 Overview Table 1.3.1-10 Error Addition (Cont’d) Item Specifications Error on LSB&MSB Adds the specified symbol error. This is available only when Coding is PAM4. An error is inserted to make the PAM4 signal change by one level only. Source Internal, External-Trigger (Rise edge trigger), External-Disable (L: Disable)
Page 53 Specifications Table 1.3.1-10 Error Addition (Cont’d) Item Specifications PCIe6 FEC Symbol Error This is available only when Coding is PAM4.* An error is inserted to make the PAM4 signal change by one level only. PAM4: An error is inserted every 4 or 12 PAM4 symbols. Source Internal, External-Trigger (Rise edge trigger), External-Disable (L: Disable)
Page 54 Chapter 1 Overview Table 1.3.1-10 Error Addition (Cont’d) Item Specifications PCIe6 FEC Symbol Error (Cont’d) Type1: Error Addition Method Level 0 Level 1, Level 1 Level 2, Level 2 Level 3, Level 3 Level 2 Type2: Level 0 Level 1, Level 1 Level 2, Level 2 Level 1, Level 3...
Page 55 Specifications Table 1.3.1-11 Data Output Item Specifications* Number of Outputs 2 (Data, XData) Cannot be varied independently Waveform NRZ, PAM4 NRZ Eye Amplitude Setting Range NRZ: 70 to 800 mVp-p, 2 mV step (Single-Ended) Accuracy When using the J1789A: ±35 mV ±12 % (Single-Ended)* When using the J1790A: ±35 mV ±12 % (Single-Ended)* PAM4 Eye Amplitude PAM4 (0/3 Level)
Page 56 Chapter 1 Overview *4: Setting Range ≤ 600 mVp-p (≤ 58.2 Gbit/s, when the Options 002, y12, 003, y13 and y23 are installed *5: Setting Range ≤ 550 mVp-p (≤ 64.2 Gbit/s, when the Options 003, y13 and y23 are installed) *6: When PAM4 output signal is directly input to the ED, the lower limit for the error-free amplitude depends on the performance of the ED used.
Page 57 Specifications Table 1.3.1-11 Data Output (Cont'd) Item Specifications* Half Period Jitter Setting Range –20.0 to +20.0, 0.1 step Accuracy Typ. ±0.04 UI* Jitter Measurement NRZ, conditions Bit rate 32.1 Gbit/s (When the Option 001 is installed), 58.2 Gbit/s (When the Options 002 and y12 are installed), 64.2 Gbit/s (When the Options 003, y13 and y23 are installed) Eye Amplitude 0.5 Vp-p (Single-Ended) At a constant temperature between 20 and 30 °C, measure with a 70-...
Page 58 Chapter 1 Overview installed), 1.0 Vp-p (Differential), refer to the IEEE P802.3bs for equation to calculate. *18: PAM4, 26.5625 Gbaud (When the Option 001 is installed), 53.125 Gbaud (When the Options 002, y12, 003, y13 and y23 are installed), 1.0 Vp-p (Differential), refer to the IEEE P802.3cd for equation to calculate.
Page 59 Specifications Table 1.3.1-11 Data Output (Cont'd) Item Specifications* Channel Emulator* Normal: Outputs the PPG Data signal whose waveform emulates the connected transmission line with the loaded S parameter. Inverse: Outputs the PPG Data signal whose inverse characteristics emulate the transmission line with the loaded S parameter. Response Normal, Inverse S-Parameter file...
Page 60 Chapter 1 Overview *22: It is assumed to use for the purpose of compensating the loss of the transmission line. The following graph shows typical limits for adjustable insertion loss. However, it does not mean that all the responses emulated from the S-Parameter file are compensated as the graph shows.
Page 61 Specifications Table 1.3.1-12 Clock Output Item Specifications* Frequency Full Rate Operation Baud Rate = Clock Output Frequency 2.4 to 32.1 GHz (Option 001) Half Rate Operation Baud Rate = (Clock Output Frequency) × 2 1.2 to 16.05 GHz (Option 001) 1.2 to 29.1 GHz (When the Options 002 and y12 are installed) 1.2 to 32.1 GHz (When the Options 003, y13 and y23 are installed) Quarter Rate...
Page 62 Chapter 1 Overview Table 1.3.1-14 Jitter Tolerance Item Specifications Jitter tolerance For NRZ output, Bit rate: 32.1 Gbit/s (Option 001) 58.2 Gbit/s (When the Options 002 and y12 are installed) 64.2 Gbit/s (When the Options 003, y13 and y23 are installed) Pattern: PRBS2...
Page 63 Specifications Table 1.3.1-14 Jitter Tolerance (Cont’d) Item Specifications Jitter tolerance 58.2 Gbit/s, 64.2 Gbit/s (Cont’d) 10000 Max. modulation amplitude Specification 1000 100k 100M 1000M Modulation Frequency [Hz] Modulation Max. modulation Specification frequency [Hz] amplitude [UIp-p] [UIp-p] 2 000 1 000 7 500 2 000 1 000...
Page 64 Chapter 1 Overview Table 1.3.1-15 Multichannel Operation* Item Specifications Multi-Module A function to synchronize timing of generating patterns among Synchronization multiple modules *2, *3, *4, *5, *6 Baud Rate ≤ 32.1 Gbaud: Capable of synchronizing bit generation timing with an accuracy of less than 1 UI Baud Rate >...
Page 65 Specifications Table 1.3.1-15 Multichannel Operation* (Cont’d) Item Specifications Only the items to be changed when Multi-Module Synchronization is Output set are described. Phase setting range –64 000 to +64 000 mUI* Phase setting resolution 2 mUI* Pattern Data length When CH Combination is set: 4 to 536,870,912 bits, 2 bits step When CH Synchronization is set: same as Sync OFF...
Page 66 Chapter 1 Overview Table 1.3.1-16 General Item Specifications Dimensions 21 mm (H), 234 mm (W), 175 mm (D) Excluding protrusions Mass 2.5 kg max. Operating Temperature 15 to 30 °C MP1900A’s ambient temperature. MU196020A shall operate when installed. Storage Temperature –20 to 60 °C MU196020A installed to MP1900A shall comply with MIL-T-28800E Class 5.
Page 67: Specifications For Mu196040A
Specifications 1.3.2 Specifications for MU196040A Table 1.3.2-1 Operating Baud Rate Item Specifications Operating Baud Rate When the Option 001 is installed. PAM4 input: 2.4 to 32.1 Gbaud NRZ input: 2.4 to 32.1 Gbit/s Table 1.3.2-2 System Clock Item Specifications System Clock External, Recovered Clock (When the Option 022 is installed) External: Clock input from the Ext Clock Input connector...
Page 68 Chapter 1 Overview Table 1.3.2-3 Data Input Item Specifications Number of inputs 2 (Data, XData) (Differential) Input Condition Single-Ended, Differential 50 Ohm, Differential 100 Ohm When set to Differential 50 Ohm or Differential 100 Ohm: Independent, Tracking, Alternate* When set to Alternate: Data-XData, XData-Data* When set to Single-Ended: Data, XData*...
Page 69 Specifications Table 1.3.2-3 Data Input (Cont’d) Item Specifications Single-Ended , Mark Ratio1/2, when connecting directly to the Sensitivity MU196020A with J1789A. When the Option-001 is installed, 34VKF50A shall be included. At a constant temperature between 20 and 30 °C Eye Amplitude NRZ, PRBS31 Typ.
Page 70 Chapter 1 Overview Table 1.3.2-3 Data Input (Cont’d) Item Specifications Stressed Margin* Stressed Eye Height PAM4 0/1 1/2 2/3 Level, QPRBS13-CEI, Eye Height where BER is 1E– 06, when using External Clock ≥ 32 mV* Stressed Eye Width PAM4 0/1 1/2 2/3 Level, QPRBS13-CEI, Eye Width where BER is 1E–06, when using External Clock ≥...
Page 71 Specifications Table 1.3.2-4 Clock Input Item Specifications Operation Baud Rate = Clock Input Frequency (When the Option 001 is External Clock Input installed) Number of inputs 1 (Single-Ended) Frequency range When the Option 001 is installed: 2.4 to 32.1 GHz Amplitude 0.3 to 1.0 Vp-p (–6.5 to +4.0 dBm) (Input Frequency ≤...
Page 72 Chapter 1 Overview Table 1.3.2-7 Pattern Detection Item Specifications PRBS Pattern length –1 (n = 7, 9, 10, 11, 13, 15, 20, 23, 31) Mark ratio 1/2, 1/2inv PRBS generator n=7: 1 + X polynomial n=9: 1 + X n=10: 1 + X n=11: 1 + X...
Page 73 Specifications Table 1.3.2-8 Pattern Sequence Item Specifications Sequence Repeat, Burst Repeat Continuous Pattern Burst This is available only when Coding is NRZ. Source Internal, External-Enable (Aux Input), External-Trigger (Aux Input) Delay Internal: 0 to 2 147 483 640 bits, 8 bits step External-Trigger, External-Enable: 0 to 2 147 483 520 bits, 8 bits step Adjust Method:...
Page 74 Chapter 1 Overview Table 1.3.2-9 Measurement Item Specifications Counter Error Rate (ER) Total: 0.000 1E–18 to 1.000 0E00 Error Count (EC) Total: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 Error Interval: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 %Error Free Interval: 0.000 0 to 100.000 0 Error Rate (ER) Insertion (INS):...
Page 75 Specifications Table 1.3.2-9 Measurement (Cont’d) Item Specifications The following are available when the Option x41 SER Measurement is Counter (Cont’d) installed. The following are available only for PAM4 (Diagnostics Mode OFF) measurement. Symbol Error Rate (SER): 0.000 1E–18 to 1.000 0E00 Symbol Error Count (SEC): 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 Symbol Error Interval: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17...
Page 76 Chapter 1 Overview Table 1.3.2-9 Measurement (Cont’d) Item Specifications Counter (Cont’d) Level 2 3 EC: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 Level 2 1 EC: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 Level 2 0 EC: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 Level 2...
Page 77 Specifications Table 1.3.2-10 Error Analysis Item Specifications Block Window Excludes the specified data pattern from measurement. Setting resolution Pattern length (bits) Step (bits) 2 to 2 097 152 2 097 153 to 4 194 304 4 194 305 to 8 388 608 8 388 609 to 16 777 216 16 777 217 to 33 554 432 33 554 433 to 67 108 864...
Page 78 Chapter 1 Overview Table 1.3.2-13 Jitter Tolerance Item Specifications Jitter tolerance For NRZ output Bit rate: 32.1 Gbit/s Pattern:PRBS2 –1 With MU181500B, SSC with frequency of 33 kHz and deviation of 5300 ppm can be applied simultaneously with RJ with amplitude of 0.3 UI. These specifications are defined assuming the following conditions: Loopback connection to the MU196020A, at a constant temperature between 20 and 30 °C.
Page 79 Specifications Table 1.3.2-14 Clock Recovery Item Specifications* Operating bit rate NRZ: 25.5 to 32.1 Gbit/s PAM4: 25.5 to 32.1 Gbaud Setting range 25.500 000 to 32.100 000 Gbaud, 0.000 001 Gbaud step Supported standard For NRZ mode and baud rate Standard Bit Rate [Gbit/s] Remarks...
Page 80 Chapter 1 Overview Table 1.3.2-14 Clock Recovery (Cont’d) Item Specifications Jitter Tolerance At the bit rate of 28.05 Gbaud, conforming to Jitter Tolerance Mask defined by the “32G FC standard”. The following masks are taken as Clock Recovery* typical values: 0.01 100k 10M 100M 1000M...
Page 81 Specifications *5: Typical value, specified at a constant temperature between 20 and 30 °C. Table 1.3.2-15 General Item Specifications Dimensions 21 mm (H), 234 mm (W), 175 mm (D), Excluding protrusions Mass 2.5 kg max. Operating temperature 15 to 30 °C MP1900A’s ambient temperature.
Page 82: Specifications For Mu196040B
Chapter 1 Overview 1.3.3 Specifications for MU196040B Table 1.3.3-1 Operating Baud Rate Item Specifications Operating Baud Rate When the Option 001 is installed. PAM4 input: 2.4 to 32.1 Gbaud NRZ input: 2.4 to 32.1 Gbit/s When the Option 002 or y12 is installed. PAM4 input: 2.4 to 58.2 Gbaud* NRZ input: 2.4 to 64.2 Gbit/s* When BERT for PCIe1-6 is selected:...
Page 83 Specifications Table 1.3.3-3 Data Input Item Specifications Number of inputs 2 (Data, XData) (Differential) Input Condition Single-Ended, Differential 50 Ohm, Differential 100 Ohm When set to Differential 50 Ohm or Differential 100 Ohm: Independent, Tracking, Alternate* When set to Alternate: Data-XData, XData-Data* When set to Single-Ended: Data, XData*...
Page 84 Chapter 1 Overview *6: Bit rate >32.1 Gbit/s *7: 0/3 Level, PRBS31, Mark Ratio1/2, with connected to the MU196020A using an attenuator, with Emphasis adjusted so that the Eye Height meets the specification MP1900A Data Output MU196020A Data Input MU196040B Example of waveform input to MU196040B when baud rate is 32.1 Gbaud 0.3 to 1.0 Vp-p...
Page 85 Specifications Table 1.3.3-3 Data Input (Cont’d) Item Specifications Single-Ended , Mark Ratio1/2, PRBS31, when connecting directly to the Sensitivity MU196020A using J1789A and an attenuator, Emphasis ON, unused connectors on the MU196020A and MU196040B are terminated, At a constant temperature between 20 and 30 °C Eye Amplitude Typ.
Page 86 Chapter 1 Overview Table 1.3.3-3 Data Input (Cont’d) Item Specifications Stressed Margin Stressed Eye Height PAM4 0/1 1/2 2/3 Level, QPRBS13-CEI, Eye Height where BER is 1E– 06, when using External Clock ≥ 32 mV* ≥ 37 mV* Stressed Eye Width PAM4 0/1 1/2 2/3 Level, QPRBS13-CEI, Eye Width where BER is 1E–06, when using External Clock ≥...
Page 87 Specifications MP1900A Data Output J1789A 40 cm V Cable MU196020A Data Input J1800A MU196040B ISI Board J1789A 40 cm V Cable At a constant temperature between 20 and 30 °C, measure with a 70-GHz bandwidth sampling oscilloscope with residual jitter of less than 200 fs (RMS).
Page 88 Chapter 1 Overview *19: When the Option x11 is installed. *20: 53.125 Gbaud, Calculated from the following three: ● The BER result obtained when DFE is OFF under the condition of *18. ● The BER result obtained when DFE is OFF under the condition of *18 and 1.8 dB additional loss.
Page 89 Specifications Table 1.3.3-7 Pattern Detection Item Specifications PRBS Pattern length –1 (n = 7, 9, 10, 11, 13, 15, 20, 23, 31) Mark ratio 1/2, 1/2inv PRBS generator n=7: 1 + X polynomial n=9: 1 + X n=10: 1 + X n=11: 1 + X n=13:...
Page 90 Chapter 1 Overview Table 1.3.3-7 Pattern Detection (Cont’d) Item Specifications Coding NRZ, PAM4 Normal, Invert PAM4 Gray Coding ON, OFF* PAM4 Precoding ON, OFF* (1/(1 + D) mod 4)* PAM4 Inverse Gray Coder ON, OFF* PAM4 Pre Code ON, OFF* Remover* Input Signal Decoder ON, OFF...
Page 91 Specifications Table 1.3.3-7 Pattern Detection (Cont’d) Item Specifications PAM4 Standard Pattern Standard-compliant PAM4-mode patterns QPRBS13-CEI, QPRBS31-CEI IEEE IEEE802.3bs/cd: PRBS13Q, PRBS31Q, SSPRQ, Square Wave IEEE802.3bj: QPRBS13, JP03A, JP03B, Transmitter Linearity InfiniBand PRBS13Q (InfiniBand), PRBS23Q, PRBS31Q (InfiniBand) Fibre Channel PRBS31Q (Fibre Channel) RS-FEC RS-FEC Scrambled Idle 50G 1Lane* RS FEC Scrambled Idle 100G 1Lane*...
Page 92 Chapter 1 Overview Table 1.3.3-8 Pattern Sequence Item Specifications Sequence Repeat, Burst Repeat Continuous Pattern Burst This is available only when Coding is NRZ. Source Internal, External-Enable (Aux Input), External-Trigger (Aux Input) Delay Internal: 0 to 2 147 483 640 bits, 8 bits step External-Trigger, External-Enable: 0 to 2 147 483 520 bits, 8 bits step Adjust Method:...
Page 93 Specifications Table 1.3.3-9 Measurement (Cont’d) Item Specifications Counter (Cont’d) MSB Error Rate (ER) Total: 0.000 1E–18 to 1.000 0E00 MSB Error Count (EC) Total: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 MSB Error Interval* 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 MSB %Error Free Interval* : 0.000 0 to 100.000 0 MSB Error Rate (ER) Insertion (INS):...
Page 94 Chapter 1 Overview Table 1.3.3-9 Measurement (Cont’d) Item Specifications Counter (Cont’d) The following are available when the Option z41 SER Measurement is installed. The following are available only for PAM4 (Diagnostics Mode OFF) measurement. Symbol Error Rate (SER): 0.000 1E–18 to 1.000 0E00 Symbol Error Count (SEC): 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 Symbol Error Interval: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17...
Page 95 Specifications Table 1.3.3-9 Measurement (Cont’d) Item Specifications Counter (Cont’d) Level 2 3 EC: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 Level 2 1 EC: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 Level 2 0 EC: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 Level 2 EC Total: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17...
Page 96 Chapter 1 Overview Table 1.3.3-9 Measurement (Cont’d) Item Specifications Counter (Cont’d) The following items are available only when the Option w42 FEC Analysis is installed. Uncorrectable Codeword Error Rate (UCWER): 0.000 1E–18 to 1.000 0E00 Uncorrectable Codeword Error Count (UCWEC): 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 Uncorrectable Codeword Error Interval: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17...
Page 97 Specifications Table 1.3.3-9 Measurement (Cont’d) Item Specifications The following items are available only when the BERT for PCIe1-6 Counter (Cont’d) Application is selected and the Option w43 FEC Analysis for PCIe6 is installed. Flit Error Rate (FER): 0.000 1E–18 to 1.000 0E00 Flit Error Count (FEC): 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 Flit Error Interval:...
Page 98 Chapter 1 Overview Table 1.3.3-9 Measurement (Cont’d) Item Specifications Counter (Cont’d) Details-Result FEC FEC Symbol Error Count N = 0 to Over8 Flit Rate: 0.000 1E–18 to 1.000 0E00 N = 0 to Over8 Flit Count: 0 to 9 999 999, 1.000 0E07 to 9.999 9E17 N = 0 to Over8 ECC Group Rate: 0.000 1E–18 to 1.000 0E00 N = 0 to Over8 ECC Group Count:...
Page 99 Specifications Table 1.3.3-9 Measurement (Cont’d) Item Specifications Input Signal Decoder Displays the coding status during PAM4 mode error measurement. Indicator Raw Signal: Displays error measurement results of input data without decoding it. Decoded Signal: Displays error measurement results of decoded input data.
Page 100 Chapter 1 Overview Table 1.3.3-10 Error Analysis Item Specifications Bit Mask (Block Window) Excludes the specified data pattern from measurement.* Setting resolution The resolution is set depending on the pattern length as follows: Pattern length (bits) Setting resolution (bits) 2 to 2 097 152 2 097 153 to 4 194 304 4 194 305 to 8 388 608 8 388 609 to 16 777 216...
Page 101 Specifications Table 1.3.3-10 Error Analysis (Cont’d) Item Specifications NRZ, PAM4 (Only FEC Symbol Capture is available when LSB/MSB Capture Diagnostics is set to ON.) PAM4 is available when the Option z41 SER Measurement is installed. Capture Mode Sync Mode Capture Performs error judgment.
Page 102 Chapter 1 Overview Table 1.3.3-10 Error Analysis (Cont’d) Item Specifications Capture (Cont’d) Auto Launch Select the result screen you want to display automatically when data is captured. ● Capture Data Displays the captured pattern data numerically or by a string (Bin, Hex, Symbol).
Page 103 Specifications *6: Consecutive Flit Error Detect: Starts capturing when the number of consecutive flit errors equals to or exceeds the threshold. Table 1.3.3-10 Error Analysis (Cont’d) Item Specifications Capture (Cont’d) Trigger Position After the Trigger, Around the Trigger, Before the Trigger After the Trigger and Before the Trigger cannot be selected when Capture Mode is FEC Symbol Capture or PCIe6 FEC Symbol Capture.
Page 104 Chapter 1 Overview Table 1.3.3-10 Error Analysis (Cont’d) Item Specifications Capture (Cont’d) PCIe6 FEC Symbol Capture Setting PCIe6 Standard x1 Link Common CLK/SRNS Mode x2 Link Common CLK/SRNS Mode x4 Link Common CLK/SRNS Mode x8 Link Common CLK/SRNS Mode x16 Link Common CLK/SRNS Mode x1 Link SRIS Mode x2 Link SRIS Mode x4 Link SRIS Mode...
Page 105 Specifications Table 1.3.3-10 Error Analysis (Cont’d) Item Specifications Capture (Cont’d) Capture Result (Cont’d) Capture Data (Cont’d) Error display NRZ: Insertion Error, Omission Error When the input signal decoder is OFF: PAM4(Symbol): Lower Eye Error, Middle Eye Error, Upper Eye Error, Middle/Lower Eye Error, Upper/Middle Eye Error, Upper/Middle/Lower Eye Error When the input signal decoder is ON:...
Page 106 Chapter 1 Overview Table 1.3.3-10 Error Analysis (Cont’d) Item Specifications Capture (Cont’d) File Save Saves the captured results and pattern to a file. NRZ: BIN/HEX Text: Captured result file (It can be opened in the Capture Data screen.) BIN/HEX Text(export): Pattern file including error information (It can be opened in Pattern Editor.) PAM4: Symbol Text:...
Page 107 Specifications Table 1.3.3-11 Auto Measurement Item Specifications Bath-Tub NRZ/PAM4: Available* Eye Contour NRZ/PAM4: Available* Auto Adjust NRZ: Vth direction only* PAM4: MSB Vth direction only* Auto Search NRZ: Available* PAM4 (LSB/MSB Diagnostics OFF/ON): Available* Supports adjustment of PRBS Inv, Logic (MSB, LSB), Gray Coder, Advanced Search Inverse Gray Coder, Eye Threshold (Middle, Upper, Lower), Delay, DFE and LFEQ.*...
Page 108 Chapter 1 Overview Table 1.3.3-12 Variable Clock Delay Item Specifications Phase variable range –1000 to +1000 mUI, 2 mUI step Accuracy ±50 mUIp-p* (Baud rate ≤32.1 Gbaud) ±100 mUIp-p* (Baud rate >32.1 Gbaud) mUI – ps switching Available (internally converted into ps) Calibration Available (when jitter modulation is off) Calibration indicator...
Page 109 Specifications Table 1.3.3-13 Jitter Tolerance Item Specifications For NRZ input Bit rate: 32.1 Gbit/s, 64.2 Gbit/s* Pattern:PRBS2 –1 32.1 Gbits: With MU181500B, SSC with frequency of 33 kHz and deviation of 5300 ppm can be applied simultaneously with RJ with amplitude of 0.3 UI. 64.2 Gbits: With MU181500B, SSC with frequency of 33 kHz and deviation of 3300 ppm can be applied simultaneously...
Page 110 Chapter 1 Overview Table 1.3.3-13 Jitter Tolerance (Cont’d) Item Specifications For NRZ input (Cont’d) 64.2 Gbit/s 10000 Max. modulation amplitude Specification 1000 100k 100M 1000M Modulation Frequency [Hz] Modulation Max. modulation Specification frequency [Hz] amplitude [UIp-p] [UIp-p] 2 000 1 000 7 500 2 000 1 000...
Page 111 Specifications Table 1.3.3-13 Jitter Tolerance (Cont’d) Item Specifications For PAM4 input Baud rate: 32.1 Gbaud* , 58.2 Gbaud* Pattern:PRBS31Q 32.1 Gbaud: With MU181500B, SSC with frequency of 33 kHz and deviation of 5300 ppm can be applied simultaneously with RJ with amplitude of 0.3 UI. 58.2 Gbaud: With MU181500B, SSC with frequency of 33 kHz and deviation of 3300 ppm can be applied simultaneously...
Page 112 Chapter 1 Overview Table 1.3.3-13 Jitter Tolerance (Cont’d) Item Specifications For PAM4 input (Cont’d) 58.2 Gbaud 10000 Max. modulation amplitude Specification 1000 100k 100M 1000M Modulation Frequency [Hz] Modulation Max. modulation Specification frequency [Hz] amplitude [UIp-p] [UIp-p] 2 000 1 000 7 500 2 000 1 000...
Page 113 Specifications Table 1.3.3-14 Clock Recovery Item Specifications* Operating Baud rate When the Option x21 is installed. NRZ: 2.4 to 29.0 Gbit/s PAM4: 2.4 to 29.0 Gbaud When the Option x22, or x21 + y24 is installed. NRZ: 2.4 to 32.1 Gbit/s PAM4: 2.4 to 32.1 Gbaud When the Option x23 is installed.
Page 114 Chapter 1 Overview Table 1.3.3-14 Clock Recovery (Cont’d) Item Specifications* Supported standard and For NRZ mode baud rate Standard Bit Rate [Gbit/s] Remarks CEI-56G 56.000 000 * 100G ULH 32.100 000 * PCIe5 32.000 000 * 32G FC 28.050 000 * CEI-28G 28.000 000 * 100G OTU4...
Page 115 Specifications Table 1.3.3-14 Clock Recovery (Cont’d) Item Specifications* Supported standard and For NRZ mode baud rate Standard Bit Rate [Gbit/s] Remarks USB4 Gen2 10.000 000 * InfiniBand QDR 10.000 000 * USB3.1 Gen2 10.000 000 * OC-192/STM-64 9.953 280 * 8G FC 8.500 000 * DisplayPort HBR3...
Page 116 Chapter 1 Overview Table 1.3.3-14 Clock Recovery (Cont’d) Item Specifications* Supported standard and For PAM4 mode baud rate (Cont’d) Standard Baud Rate [Gbaud] Remarks CEI 112G 56.000 000 * 400GAUI-4 (400GbE (53.1 × 4)) 53.125 000 * 200GAUI-2 53.125 000 * 100GAUI-1 53.125 000 * PCIe6...
Page 117 Specifications Table 1.3.3-14 Clock Recovery (Cont’d) Item Specifications* Target loop band When the Option x21, x22, or x21 + y24 is installed. 25.5 to 32.1 G* Baud rate / 1667 Baud rate / 2578 Baud rate / 6640 Jitter Tolerance 2.4 to 25.499 999 G Baud rate / 1667 Baud rate / 2578...
Page 118 Chapter 1 Overview Table 1.3.3-14 Clock Recovery (Cont’d) Item Specifications Jitter Tolerance NRZ input* At the bit rate of 58.0 Gbit/s, conforming to Jitter Tolerance Mask defined by the “CEI 56G Jitter Tolerance Mask”. The following masks are taken as nominal values: 0.01 100k 10M 100M 1000M...
Page 119 Specifications Table 1.3.3-14 Clock Recovery (Cont’d) Item Specifications Jitter Tolerance (Cont’d) PAM4 input* At the bit rate of 53.125 Gbaud, conforming to Jitter Tolerance Mask defined by the “CEI-112G-VSR Jitter Tolerance Mask”. The following masks are taken as nominal values: 0.01 100k 10M 100M 1000M...
Page 120 Chapter 1 Overview Table 1.3.3-15 General Item Specifications Dimensions 21 mm (H), 234 mm (W), 175 mm (D), Excluding protrusions Mass 2.5 kg max. Operating temperature 15 to 30 °C MP1900A’s ambient temperature. MU196040B shall operate when installed. Storage temperature –20 to 60 °C MU196040B installed to MP1900A shall comply with MIL-T-28800E Class 5.
Page 121: Specifications For Mu196060A
*2: 32.0 Gbaud PAM4, 16.0, 32.0 Gbit/s NRZ, Differential, Modified Compliance Pattern, MU196020A + MU195050A + J1790A, MU196060A Clock Recovery, SSC 5300 ppm Down spread *3: 19.0 to 32.1 Gbaud PAM4/NRZ, Differential, PRBS31, MU196020A + MU195050A + J1790A, MU196060A Clock Recovery, SSC OFF *4: 16.0, 32.0 Gbit/s, Differential, Modified Compliance Pattern,...
Page 122 Chapter 1 Overview Table 1.3.4-2 Equalizer Item Specifications Ideal frequency response (Design value) Loss Compensation NRZ: 30 dB at 16 GHz* Compensation value satisfying BER < 1E–12 with respect to PCIe 5.0-compliant loss PAM4: 14 dB at 16 GHz* Compensation value satisfying BER < 1E-6 (Typ. BER 1E-8) with respect to PCIe 5.0-compliant loss 10 dB at 13.3 GHz * Compensation value satisfying BER <...
Page 123 Specifications *2: 32.0 Gbaud 0.8 Vp-p Differential, Modified Compliance Pattern kHz 5300 ppm Down spread SSC *3: 26.5625 Gbaud 0.8 Vp-p Differential, PRBS31, SSC OFF *4: EQ = Set value. Defined by the difference between 16 GHz and 10 MHz and in the range of –29.0 to 0.0 dB. Temperature fluctuation after setting is defined to be within ±2.5 °C.
Page 124 Chapter 1 Overview Table 1.3.4-4 Clock Output Item Specifications Number of Outputs 1 (Single-Ended) Frequency 1.25 GHz, 2.5 GHz, 4 GHz (MX183000A PCIe Link Training only) 8 GHz, 9.5 to 16.05 GHz (Half rate clock) * Amplitude 0.3 to 1.0 Vp-p (Fixed) ON/OFF ON/OFF switching available* Jitter...
Page 125 Specifications Table 1.3.4-5 Clock Recovery Item Specifications* 2.5 Gbit/s, 5 Gbit/s, 8 Gbit/s for NRZ (MX183000A PCIe Link Training Operating Baud Rate only) 16 Gbaud, 19.0 Gbaud to 32.1 Gbaud for NRZ and PAM4 Setting Range Same as the operating baud rate Setting Step 1 kbaud step or 1 kbit/s step PPG Operating baud rate...
Page 126 Chapter 1 Overview *1: When the Option x01 is installed *2: PRBS pattern, Mark ratio 1/2 (in PAM4 mode, MSB Mark Ratio), PCIe Compliance Pattern, Modified Compliance Pattern, and Training Sequence Pattern *3: 16 Gbit/s, 32 Gbit/s, 32 Gbaud When loopback-conneted to MU196020A and MU196040B, and Data pattern (PCIe Compliance Pattern, Modified Compliance Pattern, or Training Sequence Pattern) 1-110...
Page 127 Specifications Table 1.3.4-5 Clock Recovery (Cont’d) Item Specifications* Jitter tolerance (Cont’d) PAM4 input 32.0 Gbaud SSC 33 kHz, 5300 ppm, conforming to Jitter Tolerance Mask defined by the “PCIe 6.0 Jitter Tolerance Mask”. The following masks are taken as typical values: Modulation frequency JTOL Mask (UIp-p) (Hz)
Page 128 Chapter 1 Overview Table 1.3.4-6 General Item Specifications Dimensions 21 mm (H), 234 mm (W), 175 mm (D) For one Compact-PCI slot, excluding protrusions Mass 1.0 kg max. Operating Temperature 15 to 35 °C MP1900A’s ambient temperature. Storage Temperature –20 to 60 °C 1-112.
Page 129: Chapter 2 Before Use
Before Use This chapter describes preparations required before using the MP1900A modules. Installation to MP1900A ..........2-2 How to Operate Application ......... 2-2 Preventing Damage ............ 2-3...
Page 130: Installation To Mp1900A
Chapter 2 Before Use 2.1 Installation to MP1900A For information on how to install the MP1900A modules to the MP1900A and how to turn on the power, refer to Chapter 3 “Preparation before MP1900A Signal Quality Analyzer-R Operation Manual Use” in the 2.2 How to Operate Application The modules connected to the MP1900A are controlled by operating the MX190000A Signal Quality Analyzer-R Control Software (hereinafter,...
Page 131: Preventing Damage
Preventing Damage 2.3 Preventing Damage Always observe the ratings when connecting to the input and output connectors of the MP1900A modules. If an out-of-range signal is input, the MP1900A modules may be damaged. CAUTION • When signals are input to the MP1900A modules, avoid excessive voltage beyond the rating.
Page 132 Chapter 2 Before Use CAUTION • To protect the MP1900A modules from electrostatic discharge failure, a conductive sheet should be placed onto the workbench, and the operator should wear an electrostatic discharge wrist strap. Always ground the wrist strap to the workbench antistatic mat or the frame ground of the MP1900A modules.
Page 133 Preventing Damage Set output ON/OFF after power completing connections. 50 Ω To protect DUT and PPG MP1900A MU196020A Coaxial cable Coaxial cable Bias-T Do not connect/disconnect while DC voltage impressed. Figure 2.3-1 Bias-T Connection Example...
Page 134 Chapter 2 Before Use 2-6.
Page 135: Chapter 3 Panel Layout And Connectors
3.1.1 MU196020A ............3-2 3.1.2 MU196040A ............3-3 3.1.3 MU196040B ............3-4 3.1.4 MU196060A ............3-5 Inter-Module Connection ..........3-6 3.2.1 Measuring errors ..........3-8 3.2.2 Measuring errors with noise added ....3-9 3.2.3 Adding jitter to output signal ......3-11 3.2.4...
Page 136: Panel Layout
Inputs clock signals from these units: MU181000A 12.5GHz Synthesizer MU181000B 12.5GHz 4 Port Synthesizer MU181500B Jitter Modulation Source External Synthesizer* We recommend using the MG3690C series as an external synthesizer. For details about the MG3690C series, contact Anritsu or our sales representative.
Page 137: Mu196040A
Panel Layout 3.1.2 MU196040A Figure 3.1.2-1 Panel Layout (MU196040A) Table 3.1.2-1 Connectors on Panel Name Description Data Input, Input Data, Data data signals. Data Input Support both differential and single-ended input signals. AUX In Inputs auxiliary signals. Variation: External Mask, Burst AUX Out, Outputs auxiliary signals.
Page 138: Mu196040B
Chapter 3 Panel Layout and Connectors 3.1.3 MU196040B Figure 3.1.3-1 Panel Layout (MU196040B) Table 3.1.3-1 Connectors on Panel Name Description Data Input, Input Data, Data data signals. Data Input Support both differential and single-ended input signals. Be sure to terminate the unused connector with the coaxial terminator.
Page 139: Mu196060A
Be sure to use the J1917A included as standard to connect this connector to Ext Clock In of the MU196040B. Clock Output is available only when the MU196060A-x01 is installed. When the connector is not used, protect it by connecting the Open (J1341A) included as standard to it.
Page 140: Inter-Module Connection
Chapter 3 Panel Layout and Connectors 3.2 Inter-Module Connection Avoid static electricity when handling the devices. WARNING When signals are input to this MP1900A modules, avoid • excessive voltage beyond the rating. Otherwise, the circuit may be damaged. As a countermeasure against static electricity, ground •...
Page 141 MU195020A and MU183020A is 1.00 Vp-p or under. Avoid inputting the signal exceeding the maximum input level to the Data Input connector of MU196040A/B and MU196060A. Failure to do so can cause damage.
Page 142: Measuring Errors
Chapter 3 Panel Layout and Connectors 3.2.1 Measuring errors This section describes a connection example of MU196020A, MU181000B 12.5GHz 4 ports synthesizer (hereafter MU181000B), and MU196040A/B that are installed to an MP1900A. MU181000B MU196020A MU196040A/B Figure 3.2.1-1 Inter-Module Connection Example Using a coaxial cable, connect the Clock Output connector of the MU181000B and the Ext Clock Input connector of the MU196020A.
Page 143: Measuring Errors With Noise Added
Inter-Module Connection 3.2.2 Measuring errors with noise added This section describes a connection example of MU196020A, MU181000B, MU181500B Jitter Modulation Source (hereafter MU181500B), MU195050A, and MU196040A/B that are installed to an MP1900A. To connect MU196020A and the Data1 connector of MU195050A, use J1792A (optional accessory).
Page 144 Chapter 3 Panel Layout and Connectors connector of the MU195050A and the Data Input connector of the DUT. Using a coaxial cable, connect the Data Output connector of the DUT and the Data Input connector of the MU196040A/B. Also, using a coaxial cable, connect the Data Output connector of the DUT and the Data Input connector of the MU196040A/B.
Page 145: Adding Jitter To Output Signal
Inter-Module Connection 3.2.3 Adding jitter to output signal To add jitter to signals output from PAM4 PPG, use MU181000B and MU181500B. Figure 3.2.3-1 shows a connection example of MU181000B, MU181500B, MU196020A, and MU196040A/B. MU196040A/B-001 supports up to 32.1 Gbit/s and 32.1 Gbaud. MU181000B MU181500B MU196020A...
Page 146: Synchronizing Multiple Channels Of Ppg
Chapter 3 Panel Layout and Connectors 3.2.4 Synchronizing multiple channels of PPG To synchronize multiple MU196020As installed to MP1900A, use MU181000A/B or external clock. The following figure shows a connection example when synchronizing two units of MU196020A using MU181000B. MU196020A MU181000B Figure 3.2.4-1 Connection Example When Synchronizing Two Units of PPGs Connect two Clock Output connectors on MU181000B to the Ext...
Page 147 Inter-Module Connection The following figure shows a connection example when synchronizing four units of MU196020A using MU181000B and MU181500B. J1748A MU196020A MU181500B MU181000B Figure 3.2.4-2 Connection Example When Synchronizing Four Units of PPGs Connect the Clock Output connector of MU181000B and the Ext Clock Input connector of MU181500B with a coaxial cable.
Page 148: Measuring While Compensating Loss With Re-Driver
MU195050A and the Data Input connector of the device under test (DUT). Using the J1932A Coaxial Skew Matched Cable Pair (0.8m, V Connector), connect the Data Output and Output connectors Data of the MU196060A with the Data Input and XData Input connectors of the MU196040B. 3-14...
Page 149 Inter-Module Connection Using the J1917A Coaxial Semi-rigid Cable, connect the Clock Output connector of the MU196060A and the Ext Clock In connector of the MU196040B. Using a coaxial cable, connect the Data Output connector of the DUT and the Data Input connector of the MU196060A. Also, using a coaxial cable, connect the Data Output connector of the DUT and the Data Input connector of the MU196060A.
Page 150 Chapter 3 Panel Layout and Connectors 3-16.
Page 151: Chapter 4 Usage Examples
Usage Examples This chapter describes usage examples of measurement using the MP1900A modules. Evaluating Optical Components in 400GbE Transceiver ..................4-2 Evaluating Devices for 400GbE Transceiver ....4-5 Evaluating Devices for PCIe 6 ........4-8...
Page 152: Evaluating Optical Components In 400Gbe Transceiver
Chapter 4 Usage Examples 4.1 Evaluating Optical Components in 400GbE Transceiver This section explains how to evaluate optical components used in a 400GbE optical transceiver by using MU196020A and MU196040A. The optical components are as follows: • TOSA (transmitter optical subassembly) consisting of a laser diode, driver amp, EML and other parts •...
Page 153 Evaluating Optical Components in 400GbE Transceiver Measurement Connect the MP1900A and DUT to GND. Use a coaxial connector to connect the Clock Output connector of the MU181000B and the Ext. Clock In connector of the MU196020A. Use a coaxial connector to connect the Clock Out connector of the ��...
Page 154 Chapter 4 Usage Examples Test method Connect the power cord of the MP1900A. Turn on the MP1900A. Turn OFF data output. Match MU196020A data output interface to DUT's input by adjusting the amplitude and offset on the Output tab. On the Pattern tab of the MU196020A and MP196040A, set the pattern by selecting a test pattern.
Page 155: Evaluating Devices For 400Gbe Transceiver
Evaluating Devices for 400GbE Transceiver 4.2 Evaluating Devices for 400GbE Transceiver In the evaluation of SERDES for 400GbE transceiver, the jitter tolerance of the CDR (Clock Data Recovery) is measured. This test requires the emphasis settings to be configured in order to compensate the frequency characteristics of the transmission channel and devices.
Page 156 Chapter 4 Usage Examples �� Use coaxial cables to connect the Data Input connector and Data Input connector of the MU196040A to the Data Output connectors of the DUT (two connections). To input the reference clock to the DUT, connect the Sub-rate Clock Output connector of MU181500B and the Clock Input connector of the DUT with a coaxial cable.
Page 157 Evaluating Devices for 400GbE Transceiver On the Output tab of the MU196020A, set Data Output to ON, and then touch the Output button on the top of the screen to turn it from grey to green ( Adjust the threshold voltage of the MU196040A. Touch the Auto Search module function button.
Page 158: Evaluating Devices For Pcie 6
This section provides a PCIe6 Base test example with the configuration where MU196060A is installed to MP1900A. PCIe6 evaluation can be performed with MU181000B, MU181500B, MU196020A, MU196040B, MU195050A and MU196060A. For details on the connections, refer to 3.2.5 “Measuring BER while compensating loss with Re-Driver”.
Page 159 MU181500B To DUT MU196020A MU195050A To DUT MU196040B MU196060A From DUT Figure 4.3-2 Module Connection Diagram Measurement Plug the power cord of the MP1900A to a power outlet. Turn on the MP1900A. To input the reference clock to the DUT, set the Sub-rate Clock Output amplitude and division ratio of the MU181500B.
Page 160 11. While checking the BER measurement results of the MU196040B, edit the emphasis settings for the MU196020A and the CTLE settings for the MU196060A so that the BER can be optimal. 12. While checking the BER measurement results of the MU196040B, adjust the following settings to obtain values to achieve the optimal BER.
Page 161: Chapter 5 Performance Test
Chapter 5 Performance Test This chapter describes the performance testing of the MP1900A modules. Timing of Performance Tests ........5-2 Devices Required for Performance Tests ....5-3 Performance Test Items ..........5-5 5.3.1 Operating frequency range ......5-5 5.3.2 Waveform evaluation test ........ 5-7 5.3.3 Input level .............
Page 162: Timing Of Performance Tests
Chapter 5 Performance Test 5.1 Timing of Performance Tests Performance test is conducted to check that the major performance of the MP1900A modules meets the required specifications. Conduct performance tests at acceptance inspection, operation check after repair, and periodic testing (once every six months).
Page 163: Devices Required For Performance Tests
Precision Adaptor 34VFK50A For the Data Input connector of MU196040A-001 Coaxial Cable Set for J1898A For connecting MU196060A and ED * MU196060A A set of J1932A and J1917A Coaxial Skew Matched J1932A V-P, V-P, a pair of 0.8 m, for Data Output and Cable Pair (0.8m, V...
Page 164 Chapter 5 Performance Test *1: PRBS31, 26.5625 Gbit/s, 32.1 Gbit/s, when MU196040A-001 is installed. *2: PAM4 0/1 1/2 2/3 Level, PRBS31, Eye height where BER is 1E–06, when using External Clock, 26.5625 Gbaud, when MU196040A-001 is installed. *3: Used in self-loopback test. The MU195020A-001 and MU195040A-001 are required.
Page 165: Performance Test Items
Performance Test Items 5.3 Performance Test Items This section describes the following test items. ● Operating frequency range ● Waveform evaluation test ● Input level ● Input level ● Error detection ● Self-loopback test 5.3.1 Operating frequency range (1) Specifications Table 5.3.1-1 Specifications Option Specifications...
Page 166 Chapter 5 Performance Test (3) Procedure Mount the MU196020A onto the MP1900A, and turn on the MP1900A with the cables unconnected. Set the modulation mode of MU196020A and MU196040A/B to NRZ. On the Output tab of the MU196020A, set Amplitude to 0.500 Vp-p, and Offset to 0.000 V and Vth.
Page 167: Waveform Evaluation Test
Performance Test Items 5.3.2 Waveform evaluation test (1) Specifications Table 5.3.2-1 Specifications for MU196020A Item Conditions Specification Amplitude 0.07 to 0.70 Vp-p* ±35 mV ±12 % of amplitude 0.07 to 0.60 Vp-p* 0.07 to 0.55 Vp-p* −2.0 − +3.3 − Offset (Vth) ±65 mV ±10 % of offset (Vth) ±(Eye Amplitude Accuracy / 2)*...
Page 168 Chapter 5 Performance Test (2) Device connection MU181000B MU196020A J1789A or J1790A Sampling oscilloscope Trigger Input Input Figure 5.3.2-1 Connection Diagram for Waveform Test When using the MU181000A instead of MU181000B, attach the 6 dB Coaxial Attenuator to the Clock Output connector. For waveform test, use a sampling oscilloscope that has a 70 GHz band and that has a residual jitter of less than 200 fs (RMS).
Page 169 Performance Test Items (3) Procedure Mount the MU196020A onto the MP1900A, and turn on the MP1900A with the cables unconnected. Set the modulation mode of the MU196020A to NRZ. On the Output tab of the MU196020A, set as follows: Bit Rate MU196020A-001 32.100 000 MU196020A-002...
Page 170 Chapter 5 Performance Test 13. Measure the amplitude with the sampling oscilloscope, and record it. 14. On the Output tab of the MU196020A, set the value for Offset. When using MU19020A-002 and J1790A cable: –2.300 When using MU19020A-003 and J1790A cable: –2.275 Other than those above: –2.350...
Page 171 Performance Test Items oscilloscope. Be sure to connect the terminators (standard accessories) to the Output connectors to which cables are not connected. Repeat the procedure from steps 3 to 28. 5-11...
Page 172: Input Level
Chapter 5 Performance Test 5.3.3 Input level (1) Specifications Table 5.3.3-1 Specifications Option Specifications MU196040A-001 NRZ Input amplitude: 0.05 to 1.0 Vp-p PAM4 Input amplitude: 0.3 to 1.0 Vp-p Threshold voltage: −3.5 to +3.3 V MU196040B-001 NRZ Input amplitude: 0.05 to 1.0 Vp-p PAM4 Input amplitude: 0.3 to 1.0 Vp-p Threshold voltage:...
Page 173 Performance Test Items Touch Auto Search. In the Mode list, select Fine, and then select Start. Check that the threshold voltage and phase are adjusted to optimum values and that no error occurs. Set the modulation mode of MU196020A and MU196040A/B to PAM4.
Page 174 Chapter 5 Performance Test Amplitude: 0.5 Vp-p Offset: +3.05 V *3: In the Mode list, select Fine (NRZ), and then start Auto Search to adjust the threshold voltage and phase to optimum values. Table 5.3.3-3 PAM4 Input Level Test Settings (MU196040A/B) MU196020A MU196040A/B No.
Page 175: Pattern
Performance Test Items 5.3.4 Pattern (1) Specifications ● PRBS pattern (NRZ, PAM4) ● Zero Substitution pattern (NRZ) ● SSPRQ pattern (PAM4) (2) Connection Refer to Figure 5.3.3-1 for the device connection. (3) Procedure Configure the settings in the same manner as shown in steps 1 to 5 in Section 5.3.1.
Page 176: Error Detection
Chapter 5 Performance Test 10. Set the modulation mode of MU196020A and MU196040A/B to PAM4. 11. Change the test patterns of both MU196040A/B and MU196020A to SSPRQ, and check that no error occurs. 5.3.5 Error detection (1) Specifications Error rate: 0.0000 ×...
Page 177 Performance Test Items 10. Touch the Start button of the MU196040A/B. While the measurement is running for 10 seconds, select Single once on the Error Addition tab of the MU196020A. When the measurement has finished, check that the measurement results are as follows. Error rate (ER): 5.0000E−12 Error count (EC):...
Page 178: Self-Loopback Test
This differs from the slot position actually inserted into the MP1900A main unit. MU181000B MU181500B MU196020A J1792A MU195050A 34VFK50A + J1790A (0.8m V) MU196060A J1898A/J1932A (0.8m V) MU196040B J1898A/J1917A (Semi-rigid cable) Figure 5.3.6.1-1 Self-Loopback Test Connection Diagram (When Using PAM4 PPG/ED) 5-18...
Page 179 Clock and Data Recovery: Clock from MU196060A On the Pattern tab of each MU196020A and MU196040B, set as follows: Test Pattern: MCP in 128b/130b Encoding for PCIe4 Set the bitrate of MU196060A’s Clock Recovery for SSC as follows: Tracking: Unit1:Slot7:MU196020A Set the SSC of the MU181500B as follows, and set it to On.
Page 180 Advanced: Equalizer:LFE/DFE: OFF (Setup LFE/DFE of MU196040B) Equalizer:CTLE: ON (Setup CTLE of MU196060A) 18. Touch Start for the MU196040B. On the Result tab, make sure that the ER measurement result is less than 1.0E-8. Measurement when SSC=OFF 19. After performing steps 1 through 18, turn Off the SSC of the MU181500B.
Page 181 MU181000B MU181500B MU195020A J1746A MU195050A 34VKF50A + J1932A/J1790A (0.8m V) MU196060A J1898A/J1932A (0.8m V)+ 34VFK50A J1624A (0.3m) MU195040A Figure 5.3.6.2-1 Self-Loopback Test Connection Diagram (When Using SI PPG/ ED) (3) Procedure Connect the measuring instrument cables as shown in Figure 5.3.6.2-1.
Page 182 Turn on the MU195020A output, and then select Auto Search. Set as follows, and then select Start. Mode: Fine(NRZ) Adjust CTLE Gain: (Setup CTLE of MU195040A/ MU196060A) Assign Slot5 CTLE to: Slot6-1 ED (Slot5: Uses CTLE of MU196060A) On the Measurement tab of the MU195040A, set as follows:...
Page 183 Maintenance This chapter describes maintenance of the MP1900A modules. Daily Maintenance ............6-2 Cautions on Storage ........... 6-2 Transportation............. 6-3 Calibration ..............6-3...
Page 184: Chapter 6 Maintenance
Chapter 6 Maintenance 6.1 Daily Maintenance • Wipe off any external stains with a cloth damped with diluted mild detergent. • Vacuum away any accumulated dust or dirt with a vacuum cleaner. • Tighten any loose parts fixed with screws, using the specified tools. 6.2 Cautions on Storage Wipe off any dust, soil, or stain on the MP1900A modules prior to storage.
Page 185: Transportation
The recommended calibration cycle after delivery of the Signal Quality Analyzer Series is twelve months. If you require support after delivery, contact an Anritsu Service and Sales office. Contact information can be found on the last page of the printed version of this manual, and is available in a separate file on the PDF version.
Page 186 Chapter 6 Maintenance 6-4.
Page 187 Troubleshooting This chapter describes how to determine if a failure has occurred when a problem occurs during the MP1900A module operation. Problems That Occur When Replacing Modules ..7-2 Problems That Occur During Output Waveform Observation ..............7-3 Problems That Occur During Error Rate Measurement ..........
Page 188: Chapter 7 Troubleshooting
Anritsu web site (https://www.anritsu.com). If the appropriate modulus are not recognized, it may have failed. Contact an Anritsu Service and Sales office. Contact information can be found on the last page of the printed version of this manual, and...
Page 189: Problems That Occur During Output Waveform Observation
Problems That Occur During Output Waveform Observation 7.2 Problems That Occur During Output Waveform Observation Table 7.2-1 Remedies for Problems That Occur During Waveform Observation Symptom Check Item Remedy Output waveform Is the Data or Clock on the On the Output tab, set Data or Clock to be output cannot be Output tab set to ON? to ON.
Page 190: Problems That Occur During Error Rate Measurement
Chapter 7 Troubleshooting 7.3 Problems That Occur During Error Rate Measurement Table 7.3-1 Remedies for Problems That Occur During Error Rate Measurement Symptom Check Item Remedy An error occurs. Is the connection interface Check that the data rate, level, offset and with the DUT correct? termination conditions match those of the DUT.
Page 191: Synchronization Failures
Synchronization Failures 7.4 Synchronization Failures Table 7.4-1 Remedies for Synchronization Failures Item Check Item Remedy Input conditions Do the quality, status and Replace the cables with appropriate ones in the length of the connection cables following cases: comply with the specifications? •...
Page 192 Chapter 7 Troubleshooting Table 7.4-1 Remedies for Synchronization Failures (Cont’d) Item Check Item Remedy PAM4 symbol Has symbol synchronization In Diagnostics Mode, check that MSB/LSB Diff is synchronization been established between 0. If it is 0, symbol synchronization has been conditions PAM4 MSB and LSB? established.
Page 193: Appendix A Pseudo-Random Pattern
Appendix A Pseudo-Random Pattern Pseudo-Random Pattern ..........A-2 Zero-Substitution Pattern ........... A-3...
Page 194 Appendix A Pseudo-Random Pattern A.1 Pseudo-Random Pattern Table A.1-1 shows the principle of pseudo-random pattern generation. A pseudo-random pattern is expressed in an N-th degree generating polynomial, with one cycle of 2 –1. For a PRBS pattern with a cycle of –1, a pattern of successive “1s”...
Page 195 Zero-Substitution Pattern A.2 Zero-Substitution Pattern A string of successive “0s” for the number of set bits is made by substituting “0” for the pattern that follows the longest bit string of successive 0s in a PRBS pattern. In this event, if the bit immediately after the bit substituted to “0”...
Page 196 Appendix A Pseudo-Random Pattern A-4．...
Page 197 Appendix B List of Default Settings Appendix B lists the factory default settings for MU196020A, MU196040A, MU196040B, and MU196060A. To initialize all settings, select Menu → Initialize. MU196020A ..............B-2 B.1.1 PAM4 ..............B-2 B.1.2 NRZ ..............B-8 MU196040A ..............B-13 B.2.1 PAM4 ..............
Page 198: Mu196020A
Appendix B List of Default Settings B.1 MU196020A B.1.1 PAM4 Table B.1.1-1 Output Tab Main Item Secondary Item Tertiary Item Default Baud Rate Variable Baud Rate 12.500 000 Gbaud Output Data Clock Level Guard Level Guard Setup Total Amplitude 0.800 V Offset Max(Voh) 3.300 V Offset Min(Vol)
Page 199 MU196020A Table B.1.1-2 Emphasis Tab Main Item Secondary Item Tertiary Item Default Manual Setting Emphasis Standard/Preset USER De-Emphasis Preset0 Graph Total Amplitude 0.500 Vp-p Upper Eye 33.400 % Lower Eye 33.400 % Cursor2 0.000 dB Cursor1 0.000 dB Post Cursor1 0.000 dB Coefficient 0.000 000...
Page 200 Appendix B List of Default Settings Table B.1.1-3 Pattern Tab Main Item Secondary Item Tertiary Item Default Test Pattern All List PRBS Length 2^15–1 PRBS Inv MSB PRBS Inv LSB Gray Coder Pre Coder Logic MSB Logic LSB Bit Shift Data Length 4 bits...
Page 201 MU196020A Table B.1.1-3 Pattern Tab (Cont’d) Main Item Secondary Item Tertiary Item Default Test Pattern PRBS13Q, PRBS Inv MSB QPRBS13-CEI, PRBS Inv LSB QPRBS31-CEI, Gray Coder PRBS13Q Pre Coder (Infiniband) Logic MSB Logic LSB Bit Shift QPRBS13 Seed Lane 0 Gray Coder Pre Coder Logic MSB...
Page 202: Appendix B List Of Default Settings
Appendix B List of Default Settings Table B.1.1-3 Pattern Tab (Cont’d) Main Item Secondary Item Tertiary Item Default Test Pattern CP in 1b/1b Gray Coder Encoding for PCIe6 Pre Coder Logic MSB Logic LSB Seed Lane 0 MCP in 1b/1b Gray Coder Encoding for PCIe6 Pre Coder...
Page 203 MU196020A Table B.1.1-4 Error Addition Tab Main Item Secondary Item Tertiary Item Default Error Addition Error Addition Mode Bit Error on MSB Bit Error on MSB Symbol/Burst Symbol Source Internal Variation Repeat Rate 1E–3 Burst Length 1 Symbols Table B.1.1-5 Misc1 Tab Main Item Secondary Item Tertiary Item...
Page 204: Nrz
Appendix B List of Default Settings B.1.2 NRZ Table B.1.2-1 Output Tab Main Item Secondary Item Tertiary Item Default Bitrate Variable Bitrate 12.500 000 Gbit/s Output Data Clock Level Guard Level Guard Setup Amplitude 0.800 V Offset Max(Voh) 3.300 V Offset Min(Vol) –2.800 V (NRZ pattern...
Page 205 MU196020A Table B.1.2-2 Emphasis Tab Main Item Secondary Item Tertiary Item Default Manual Setting Emphasis Function Standard/Preset USER De-Emphasis Preset0 Graph Amplitude 0.500 Vp-p Cursor2 0.000 dB Cursor1 0.000 dB Post Cursor1 0.000 dB Coefficient 0.000 000 0.000 000 1.000 000 0.000 000 Channel Emulator Channel Emulator Function...
Page 206 Appendix B List of Default Settings Table B.1.2-3 Pattern Tab Main Item Secondary Item Tertiary Item Default Test Pattern All List PRBS Length 2^15–1 Mark Ratio Logic Zero Substitution Length 2^15 Zero Substitution 1 bits Length Additional Bit Logic Data Length Logic Data Editor...
Page 207 MU196020A Table B.1.2-3 Pattern Tab (Cont’d) Main Item Secondary Item Tertiary Item Default Test Pattern MCP in 128b/130b SRIS Encoding for PCIe3 SKPx1 MCP in 128b/130b EIEOS Encoding for PCIe4 MCP in 128b/130b SRIS Encoding for PCIe5 SKPx1 EIEOS Pre Coder Jitter Calibration Logic Pattern for PCIe1...
Page 208 Appendix B List of Default Settings Table B.1.2-5 Misc1 Tab Main Item Secondary Item Tertiary Item Default Pattern Sequence Repeat Gating Output Repeat Pulse Width 256 bits Delay 0 bits Burst Source Internal Data Sequence Restart Enable Period 128 000 bits Burst Cycle 128 000 000 bits Delay...
Page 209: Mu196040A
MU196040A B.2 MU196040A B.2.1 PAM4 Table B.2.1-1 Result Tab Main Item Secondary Item Tertiary Item Default Switch of setting Setting display format Gating items Input Upper Eye Threshold 0.095 V Middle Eye Threshold 0.000 V Lower Eye Threshold –0.095 V UL Threshold Delay 0 mUI...
Page 210 Appendix B List of Default Settings Table B.2.1-2 Measurement Tab Main Item Secondary Item Tertiary Item Default Gating Cycle Repeat Unit Time Time 0 day 00:00:01 Clock Count >E+10 Error Count >E+10 Current Calculation Progressive Interval 100 ms Auto Sync Auto Sync Threshold Sync Control...
Page 211 MU196040A Table B.1.2-3 Pattern Tab (Cont’d) Main Item Secondary Item Tertiary Item Default Test Pattern PRBS23Q, PRBS Inv MSB PRBS31Q, PRBS Inv LSB PRBS31Q Gray Coder (Infiniband), PRBS31Q Pre Coder (Fibre Channel) Logic MSB Logic LSB PRBS13Q, PRBS Inv MSB QPRBS13-CEI, PRBS Inv LSB QPRBS31-CEI,...
Page 212 Appendix B List of Default Settings Table B.2.1-4 Input Tab Main Item Secondary Item Tertiary Item Default Data Input Condition Single-Ended Single-Ended Data Differential 50Ohm Independent Differential 100Ohm Independent Termination Data Upper Eye Threshold 0.165 V Middle Eye Threshold 0.000 V Lower Eye Threshold –0.165 V XData...
Page 213 MU196040A Table B.2.1-6 Misc1 Tab Main Item Secondary Item Tertiary Item Default Pattern Sequence Repeat Source External -Enable AUX Input External Mask AUX Output 1/N Clock 1/N Clock (Divide ratio) 1/64 Clock Pattern Sync Position 1 symbols B-17...
Page 214: Nrz
Appendix B List of Default Settings B.2.2 NRZ Table B.2.2-1 Result Tab Main Item Secondary Item Tertiary Item Default Switch of setting Setting display format Gating items Input Data Threshold 0.000 V XData Threshold – Differential Selection Data-XData Threshold – Delay 0 mUI Gating...
Page 215 MU196040A Table B.2.2-2 Measurement Tab Main Item Secondary Item Tertiary Item Default Gating Cycle Repeat Unit Time Time 0 day 00:00:01 Clock Count >E+10 Error Count >E+10 Current Calculation Progressive Interval 100 ms Auto Sync Auto Sync Threshold Sync Control Frame Length 64 bits Frame Position...
Page 216 Appendix B List of Default Settings Table B.2.2-3 Pattern Tab Main Item Secondary Item Tertiary Item Default Test Pattern All List PRBS Length 2^15–1 Mark Ratio Logic Zero Substitution Length 2^15 Zero Substitution 1 bits Length Additional Bit Logic Data Length Logic Data Editor...
Page 217 MU196040A Table B.2.2-4 Input Tab Main Item Secondary Item Tertiary Item Default Data Input Condition Single-Ended Single-Ended Data Differential 50Ohm Independent Differential 100Ohm Independent Data Threshold 0.000 V Termination Variable 0.000 V XData Threshold 0.000 V Differential Selection Data-XData Threshold 0.000 V Clock Selection...
Page 218 Appendix B List of Default Settings Table B.2.2-6 Misc1 Tab Main Item Secondary Item Tertiary Item Default Pattern Sequence Repeat Burst Source External -Enable Delay 0 bits Enable Period 128 000 bits Burst Cycle 128 000 000 bits Auto/Manual Manual AUX Input External Mask AUX Output...
Page 219: Mu196040B
MU196040B B.3 MU196040B B.3.1 PAM4 Table B.3.1-1 Result Tab Main Item Secondary Item Tertiary Item Default Switch of setting Setting display format Gating items Input Upper Eye Threshold 0.095 V Middle Eye Threshold 0.000 V Lower Eye Threshold –0.095 V U/L Threshold Sync Low Frequency Equalizer...
Page 220 Appendix B List of Default Settings Table B.3.1-1 Result Tab (Cont’d) Main Item Secondary Item Tertiary Item Default Switch of setting PCIe6 FEC Symbol Preset x1 Link Common items CLK/SRNS Mode No SKP FEC Symbol Error Threshold in One ECC Group Consecutive FEC Symbol Error Threshold...
Page 221 MU196040B Table B.3.1-3 Pattern Tab Main Item Secondary Item Tertiary Item Default Test Pattern All List PRBS Length 2^15–1 PRBS Inv MSB PRBS Inv LSB Gray Coder Pre Coder Logic MSB Logic LSB Input Signal Decoder Data Length Gray Coder Pre Coder Logic MSB Logic LSB...
Page 222 Appendix B List of Default Settings Table B.3.1-3 Pattern Tab (Cont’d) Main Item Secondary Item Tertiary Item Default Test Pattern (Cont’d) QPRBS13 Seed Lane 0 Gray Coder Pre Coder Logic MSB Logic LSB SSPRQ, JP03A, Logic MSB JP03B, Square Wave, Logic LSB Transmitter Linearity Input Signal Decoder...
Page 223 MU196040B Table B.3.1-3 Pattern Tab (Cont’d) Main Item Secondary Item Tertiary Item Default Test Pattern (Cont’d) CP in 1b/1b Gray Coder Encoding for PCIe6 Pre Coder Logic MSB Logic LSB Seed Lane 0 SKP OS Filtering Input Signal Decoder OFF MCP in 1b/1b Gray Coder Encoding for PCIe6...
Page 224 Appendix B List of Default Settings Table B.3.1-4 Input Tab Main Item Secondary Item Tertiary Item Default Data Input Condition Single-Ended Single-Ended Data Differential 50Ohm Independent Differential 100Ohm Independent Termination Data Upper Eye Threshold 0.095 V Middle Eye Threshold 0.000 V Lower Eye Threshold –0.095 V XData...
Page 225 MU196040B Table B.3.1-5 Capture Tab Main Item Secondary Item Tertiary Item Default Capture Mode Capture Mode Sync Mode Capture State ----- Capture Result Auto Launch Capture Data Display Condition Number of Blocks Capture Area After the Trigger Trigger Match Pattern Match Pattern Length 4 symbol Notation...
Page 226 Appendix B List of Default Settings Table B.3.1-7 Logging Tab Main Item Secondary Item Tertiary Item Default BER/SER Logging Logging Cycle 00:00:05 ER (Symbol) ER (Bit) ER (MSB) ER (LSB) EC (Symbol) EC (Bit) EC (MSB) EC (LSB) Clock Loss Sync Loss B-30...
Page 227: Nrz
MU196040B B.3.2 NRZ Table B.3.2-1 Result Tab Main Item Secondary Item Tertiary Item Default Switch of setting Setting display format Gating items Input Data Threshold 0.000 V XData Threshold – Differential Selection Data-XData Threshold – Delay 0 mUI 0.000 dB Gating Cycle Repeat...
Page 228 Appendix B List of Default Settings Table B.3.2-2 Measurement Tab Main Item Secondary Item Tertiary Item Default Gating Cycle Repeat Unit Time Time 0 day 00:00:01 Clock Count >E+10 Error Count >E+10 Current Calculation Progressive Interval 100 ms Auto Sync Auto Sync Threshold Sync Control...
Page 229 MU196040B Table B.3.2-3 Pattern Tab Main Item Secondary Item Tertiary Item Default Test Pattern All List PRBS Length 2^15–1 Mark Ratio Logic Zero Substitution Length 2^15 Zero Substitution 1 bits Length Additional Bit Logic Data Length Logic Data Editor Data Length Format Hex(Byte) Edit Mode...
Page 230 Appendix B List of Default Settings Table B.3.2-3 Pattern Tab (Cont’d) Main Item Secondary Item Tertiary Item Default Test Pattern CP in 128b/130b Preset Encoding for PCIe3 No SKP CP in 128b/130b SKP OS Filtering Encoding for PCIe4 CP in 128b/130b Encoding for PCIe5 MCP in 128b/130b SRIS...
Page 231 MU196040B Table B.3.2-4 Input Tab Main Item Secondary Item Tertiary Item Default Data Input Condition Single-Ended Single-Ended Data Differential 50Ohm Independent Differential 100Ohm Independent Data Threshold 0.000 V Termination Variable 0.000 V XData Threshold 0.000 V Differential Selection Data-XData Threshold 0.000 V Equalizer Low Frequency Equalizer...
Page 232 Appendix B List of Default Settings Table B.3.2-5 Capture Tab Main Item Secondary Item Tertiary Item Default Capture Mode Capture Mode Sync Mode Capture State ----- Capture Result Auto Launch Capture Data Display Condition Number of Blocks Capture Area After The Trigger Trigger Match Pattern Match Pattern Length...
Page 233 MU196040B Table B.3.2-7 Logging Tab Main Item Secondary Item Tertiary Item Default BER/SER Logging Logging Cycle 00:00:05 ER (Total) ER (INS) ER (OMI) EC (Total) EC (INS) EC (OMI) Clock Loss Sync Loss B-37...
Page 234: Mu196060A
Appendix B List of Default Settings B.4 MU196060A Table B.4-1 32G baud NRZ/PAM4 Re-Driver Main Item Secondary Item Tertiary Item Default PAM4/NRZ switching Data/XData Output Clock Output Equalizer CTLE 0.000 dB Clock Recovery Baud Rate Variable 16.000 000 Gbit/s Tracking...
Page 235: Appendix C Performance Test Record Sheet
Appendix C Performance Test Record Sheet C.1 Performance Test Result Sheet Document number: Test Location: Date: Test person in charge: Product name: Serial number: Software version: Option: Power voltage: Power frequency: Ambient temperature °C Relative humidity Model name Serial number Instruments used Model name Serial number...
Page 236 Appendix C Performance Test Record Sheet C.2 MU196020A C.2.1 MU196020A-001 Table C.2.1-1 Operating Frequency Range Results Specification Data Data No errors occur within the range from 2.4 to 32.1 Gbit/s.* No errors occur within the range from 2.4 to 32.1 Gbaud.* Pattern PRBS, 2^31–1 Table C.2.1-2 MU196020A-001 Waveform Evaluation Test- Amplitude (NRZ) Settings...
Page 237 MU196020A Table C.2.1-5 MU196020A-001 Waveform Evaluation Test- Offset (PAM4) Settings Specification Results Offset Lower Limit Upper Limit Baud rate Data Data (Vth) 32.1 Gbaud 3.265 2.817 3.713 –2.35 –2.590 –2.111 Table C.2.1-6 MU196020A-001 Waveform Evaluation Test-Cross point (NRZ) Settings Specification Results Lower Limit Upper Limit...
Page 238 Appendix C Performance Test Record Sheet C.2.2 MU196020A-002 Table C.2.2-1 Operating Frequency Range Results Specification Data Data No errors occur within the range from 2.4 to 32.1 Gbit/s.* No errors occur within the range from 2.4 to 32.1 Gbaud.* Pattern PRBS, 2^31–1 Table C.2.2-2 MU196020A-002 Waveform Evaluation Test- Amplitude (NRZ) Settings Specification...
Page 239 MU196020A Table C.2.2-5 MU196020A-002 Waveform Evaluation Test- Offset (PAM4) Settings Specification Results Offset Lower Limit Upper Limit Baud rate Data Data (Vth) 58.2 Gbaud 3.265 2.817 3.713 –2.30* –2.489 –2.112 –2.35* –2.590 –2.111 *1: When J1790A cables are used, Amplitude 0.60 Vp-p *2: When J1789A cables are used, Amplitude 0.70 Vp-p Table C.2.2-6 MU196020A-002 Waveform Evaluation Test- Cross point (NRZ) Settings...
Page 240 Appendix C Performance Test Record Sheet C.2.3 MU196020A-003 Table C.2.3-1 Operating Frequency Range Results Specification Data Data No errors occur within the range from 2.4 to 32.1 Gbit/s.* No errors occur within the range from 2.4 to 32.1 Gbaud.* Pattern PRBS, 2^31–1 Table C.2.3-2 MU196020A-003 Waveform Evaluation Test- Amplitude (NRZ) Settings Specification...
Page 241 MU196020A Table C.2.3-5 MU196020A-003 Waveform Evaluation Test- Offset (PAM4) Settings Specification Results Offset Lower Limit Upper Limit Baud rate Data Data (Vth) 64.2 Gbaud 3.265 2.817 3.713 –2.275* –2.438 –2.112 –2.35* –2.590 –2.111 *1: When J1790A cables are used, Amplitude 0.55 Vp-p *2: When J1789A cables are used, Amplitude 0.70 Vp-p Table C.2.3-6 MU196020A-003 Waveform Evaluation Test - Cross point (NRZ) Settings...
Page 242 Appendix C Performance Test Record Sheet C.3 MU196040A Table C.3-1 Input Level Range (NRZ) Settings Results MU196020A MU196040A Specification Termi Amplitude Offset Termi Threshold Data Data nation (Vp-p) (Vth) (V) nation Voltage (V) –2.35 –2.350 No errors occur. 0.05 –0.225 –0.225 +2.95 +2.950...
Page 243 MU196040A Table C.3-3 Test Pattern (PRBS-NRZ) Settings Results MU196020A MU196040A Specification Length Logic Length Logic Data Data 2^7–1 2^7–1 No errors occur. 2^9–1 2^9–1 2^11–1 2^11–1 2^13–1 2^13–1 2^15–1 2^15–1 2^20–1 2^20–1 2^23–1 2^23–1 2^31–1 2^31–1 2^31–1 2^31–1 Table C.3-4 Test Pattern (PRBS-PAM4) Settings Results MU196020A...
Page 244 Appendix C Performance Test Record Sheet Table C.3-5 Test Pattern (Zero Substitution-NRZ) Settings Results MU196020A MU196040A Specification Length Logic Length Logic Data Data No errors occur. 2^10 2^10 2^11 2^11 2^15 2^15 2^20 2^20 2^23 2^23 2^7–1 2^7–1 2^9–1 2^9–1 2^10–1 2^10–1 2^11–1...
Page 245 MU196040B C.4 MU196040B Table C.4-1 Input Level Range (NRZ ≤32.1 Gbit/s) Settings Results MU196020A MU196040B Specification Termi Amplitude Offset Termi Threshold Data Data nation (Vp-p) (Vth) (V) nation Voltage (V) –2.35 –2.350 No errors occur. 0.05 –0.225 –0.225 +2.95 +2.950 0.05 +0.305 +0.305...
Page 246 Appendix C Performance Test Record Sheet Table C.4-3 Input Level Range (PAM4 ≤32.1 Gbaud) Settings Results MU196020A MU196040B Specification Termi Amplitude Offset Termi Threshold Data Data nation (Vp-p) (Vth) (V) nation Voltage (V) –2.35 Upper: –2.117 No errors occur. Middle: –2.350 Lower: –2.583 –2.15 Upper: –2.050...
Page 247 MU196040B Table C.4-5 Test Pattern (PRBS-NRZ) Settings Results MU196020A MU196040B Specification Length Logic Length Logic Data Data 2^7–1 2^7–1 No errors occur. 2^9–1 2^9–1 2^11–1 2^11–1 2^13–1 2^13–1 2^15–1 2^15–1 2^20–1 2^20–1 2^23–1 2^23–1 2^31–1 2^31–1 2^31–1 2^31–1 Table C.4-6 Test Pattern (PRBS-PAM4) Settings Results MU196020A...
Page 248 Appendix C Performance Test Record Sheet Table C.4-7 Test Pattern (Zero Substitution -NRZ) Settings Results MU196020A MU196040B Specification Length Logic Length Logic Data Data No errors occur. 2^10 2^10 2^11 2^11 2^15 2^15 2^20 2^20 2^23 2^23 2^7–1 2^7–1 2^9–1 2^9–1 2^10–1 2^10–1...
Page 249 MU196060A C.5 MU196060A Table C.5-1 Self-loopback (NRZ) Settings* Bitrate Differential Specification Results Amplitude (Vp-p) 16.0 Gbit/s 0.18 BER < 1E-12 32.0 Gbit/s 0.18 Modified Compliance Pattern SSC 33 KHz 5300 ppm Down spread Table C.5-2 Self-loopback (NRZ) Settings* Bitrate Differential...
Page 250 Appendix C Performance Test Record Sheet Table C.5-3 Self-loopback (PAM4) Settings* Bitrate Differential Specification Results Amplitude (Vp-p) 16.0 Gbaud BER < 1E-8 32.0 Gbaud Modified Compliance Pattern SSC 33 KHz 5300 ppm Down spread Table C.5-4 Self-loopback (PAM4) Settings* Bitrate Differential Specification Results...
Page 251 Index References are to page numbers. AUX In ..........3-2, 3-3, 3-4 SERDES ............4-5 AUX Out ...........3-2, 3-3, 3-4 Standard Configuration......... 1-5 Storage ............6-2 Base ............... 4-8 Bias-T ............2-5 TIA ..............4-2 TOSA ............. 4-2 Transportation ..........6-3 Calibration.............
Page 252: Index
Index Index-2.

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Mu196040a pam4 ed Mu196040b pam4 ed Mu196020a pam4 ppg

Anritsu MU196060A Operation Manual

Table of Contents

Chapter 1 Overview

Chapter 2 Before Use

Chapter 3 Panel Layout and Connectors

Chapter 4 Usage Examples

Chapter 5 Performance Test

Maintenance

Chapter 6 Maintenance

Troubleshooting

Chapter 7 Troubleshooting

Appendix A Pseudo-Random Pattern

Appendix B List of Default Settings

Appendix B List of Default Settings

Appendix C Performance Test Record Sheet

Quick Links

Chapters

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Summary of Contents for Anritsu MU196060A

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Table of Contents