National Instruments FlexRIO NI-7931R User Manual
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National Instruments FlexRIO NI-7931R User Manual

National Instruments FlexRIO NI-7931R User Manual

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  • Page 1 NI-7932...
  • Page 2 FlexRIO NI-7931R/7932R/7935R User Manual NI-793xR User Manual August 2015 375181B-01...
  • Page 3 11500 North Mopac Expressway Austin, Texas 78759-3504 USA Tel: 512 683 0100 For further support information, refer to the NI Services appendix. To comment on National Instruments documentation, refer to the National Instruments website at ni.com/info enter the Info Code feedback...
  • Page 4 National Instruments Corporation. National Instruments respects the intellectual property of others, and we ask our users to do the same. NI software is protected by copyright and other intellectual property laws. Where NI software may be used to reproduce software or other materials belonging to others, you may use NI software only to reproduce materials that you may reproduce in accordance with the terms of any applicable license or other legal restriction.
  • Page 5 ™ The ExpressCard word mark and logos are owned by PCMCIA and any use of such marks by National Instruments is under license. The mark LabWindows is used under a license from Microsoft Corporation. Windows is a registered trademark of Microsoft Corporation in the United States and other countries.
  • Page 6 Operation of this hardware in a residential area is likely to cause harmful interference. Users are required to correct the interference at their own expense or cease operation of the hardware. Changes or modifications not expressly approved by National Instruments could void the user’s right to operate the hardware under the local regulatory rules.

  • Page 7: Table Of Contents

    Configuring a 10 MHz Reference Clock..............4-2 Auto-loading Bitfiles on Power-up................4-3 Interactive Front Panel Communication..............4-3 Using the NI Common Instrument Design Libraries..........4-4 Using niInstr Instruction Framework ............... 4-4 Streaming Overview ..................4-4 CLIP Adapters Overview ................. 4-4 © National Instruments | vii...
  • Page 8 Contents Data Trigger Overview ..................4-4 Basic Elements Overview................. 4-5 Memory Overview.................... 4-5 Compiling LabVIEW FPGA VIs................4-5 Download, Reset, and Run Side Effects in the LabVIEW FPGA Host Interface ..4-5 Streaming ........................4-6 Flow Control ..................... 4-6 DMA Streaming....................4-7 Simulating FPGA Behavior ..................
  • Page 9 NI-793xR User Manual Appendix A CLIP Signals Appendix B Using the Fan Appendix C NI Services Glossary © National Instruments | ix...

  • Page 10: About This Manual

    IP (CLIP). LabVIEW Available at Summarizes the most effective ni.com/ High-Performance techniques for optimizing tutorial FPGA Developer’s throughput, latency, and FPGA Guide resources when using the LabVIEW FPGA Module and the RIO hardware platform. © National Instruments | xi...
  • Page 11 About This Manual Table 1. Documentation Overview (Continued) Document Location Description FPGA Module Help This document is a book within With the LabVIEW FPGA the LabVIEW Help. Access this Module and LabVIEW, you can document by navigating to create VIs that run on National Start»All Programs»National Instruments FPGA targets.

  • Page 12: Xilinx Documentation

    Transceivers User Guide describing the 7 series FPGAs GTX/GTH transceivers. Vivado Design Suite User UG903 Describes using Xilinx Guide: Using Constraints Design Constraints (XDC) in Vivado tools. All Xilinx documentation can be found at www.xilinx.com © National Instruments | xiii...

  • Page 13: Additional Resources

    About This Manual Additional Resources Table 3. FlexRIO Development Resources Development Resource Location Description FlexRIO website Contains information about ni.com/flexrio FlexRIO devices, application areas, and technical resources. FlexRIO Instrument The FlexRIO Instrument https://decibel.ni.com/ content/docs/DOC-15799 Development Library Development Library is a set of host and FPGA code that provides FPGA capabilities commonly found in...

  • Page 14: Before You Begin

    Help for more information about CLIP. LabVIEW and LabVIEW FPGA LabVIEW and LabVIEW FPGA training programming are available at . You ni.com/training can also refer to the NI LabVIEW High-Performance FPGA Developer’s Guide, available at ni.com/tutorials © National Instruments | 1-1...

  • Page 15: Xilinx Licensing Information

    Chapter 1 Before You Begin Xilinx Licensing Information Refer to the Xilinx Documentation section of About This Manual for a list of Xilinx documentation that contains important Xilinx licensing information. 1-2 | ni.com...

  • Page 16: Mounting The Ni-793Xr

    In order to obtain the maximum allowable ambient temperature as specified in your device’s specifications document, you must maintain at least 1 in. of clearance on either side of the NI-793xR. Refer to Figure 2-1 for fan clearance information. Figure 2-1. Fan Clearance © National Instruments | 2-1...
  • Page 17 Chapter 2 Mounting the NI-793xR You can mount the NI-793xR in a variety of configurations. The following table lists the ecommended mounting methods. Table 2-1. Mounting Options Method Required Accessory Kit NI Part Number Direct mounting — — Panel Panel Mount Accessory Kit 784365-01 The following sections contain instructions for the mounting methods.

  • Page 18: Mounting The Ni-793Xr Directly On A Flat Surface

    Use the dimensions shown in Figure 2-2 to drill the holes required for mounting the device. Drill clearance holes 4.5 mm in diameter. Align the device on the surface. Fasten the device to the surface with the screws. Figure 2-2. NI-793xR Dimensions © National Instruments | 2-3...

  • Page 19: Installing The Rubber Feet

    Chapter 2 Mounting the NI-793xR Installing the Rubber Feet The NI-793xR ships with optional rubber feet. Install the rubber feet to the bottom of the device, as shown in Figure 2-3. Caution Do not install rubber feet when directly mounting the NI-793xR. The rubber feet will prevent full contact between the unit and the mounting surface.

  • Page 20: Hardware Architecture

    10 FlexRIO adapter module connector Refer to Figure 3-2 for LED placement. † Refer to the NI-7931R Getting Started Guide for instructions about how to wire power to the NI-7931R. ‡ Refer to Figure 3-3 for the pinout. © National Instruments | 3-1...
  • Page 21 Chapter 3 Hardware Architecture The following figure shows the NI-7931R LEDs in more detail. Figure 3-2. NI-7931R LEDs Status Power FPGA User RT User 3-2 | ni.com...
  • Page 22 GPIO_36 S117 GPIO_53 GPIO_12 GPIO_63 GPIO_37_n S116 GPIO_54_n GPIO_13_n GPIO_64_n GPIO_37 S115 GPIO_13 GPIO_54 GPIO_64 GPIO_55_n GPIO_65_n GPIO_55 GPIO_65 GPIO_56_n GPIO_66_n GPIO_56 GPIO_66 GPIO_57_n GPIO_67_n GPIO_57 GPIO_67 Note Pins S72 and S146 are shorted together. © National Instruments | 3-3...

  • Page 23: Ni-7931R Key Features

    Chapter 3 Hardware Architecture NI-7931R Key Features The NI-7931R device includes the following key features. Refer to the NI-7931R Specifications for more details. • Kintex-7 XC7K325T FPGA • 2 GB onboard FPGA-accessible DRAM • NI Linux Real-Time (32-bit) controller • FPGA to host data transfer rates of 200 MB/s (single direction), 150 MB/s (bidirectional) •...

  • Page 24: Clocking Architecture

    The following figure illustrates the clocking circuitry on the NI-7931R. Figure 3-5. NI-7931R Clocking Diagram Adapter Module IoModSyncClock Kintex-7 FPGA 10 MHz Reference Clock 40 MHz 100 MHz 200 MHz DRAM Clock Memory 166 MHz Controller Ref Clk Enable REF IN 100 MHz Oscillator © National Instruments | 3-5...
  • Page 25 Chapter 3 Hardware Architecture NI-7932R The NI-7932R is an embedded FlexRIO controller with a LabVIEW Real-Time processor and reconfigurable FPGA. The NI-7932R includes a high-speed serial interface that uses Xilinx multi-gigabit transceiver (MGT) technology; you can reuse existing protocol IP that works with MGTs, or you can develop your own protocol IP.
  • Page 26 NI-793xR User Manual The following figure shows the NI-7932R LEDs in more detail. Figure 3-7. NI-7932R LEDs Power Status FPGA User RT User © National Instruments | 3-7...
  • Page 27 Chapter 3 Hardware Architecture The following figure shows the available signals on the NI-7932R adapter module connector. Figure 3-8. NI-7932R FPGA Connector Pinout Secondary Side Primary Side Secondary Side Primary Side +3.3V +3.3V S148 GPIO_CC_38_n S114 GPIO_CC_14_n TB_Power_Good S147 TB_Present_n GPIO_CC_38 S113 GPIO_CC_14...

  • Page 28: Ni-7932R Key Features

    FPGA to host data transfer rates of 200 MB/s (single direction), 150 MB/s (bidirectional) • Real-Time processor to USB external storage data transfer rates of 60 MB/s • Real-Time processor to SD external storage data transfer rates of 12.0 MB/s (read), 9.0 MB/s (write) © National Instruments | 3-9...
  • Page 29 Chapter 3 Hardware Architecture The following figure illustrates the key components of the NI-7932R architecture. Figure 3-9. NI-7932R Architecture Key Components Controller RT Host 1 Gig E LabVIEW NV Storage RT Clock Host VI Watch Dog Interrupts Controls/Indicators NI-Defined Bus TRIG Interfaces/Streaming IP REF IN...

  • Page 30: Clocking Architecture

    100 MHz 156.25 MHz/ 200 MHz 312.5 MHz DRAM Clock Memory 166 MHz Controller Frequency Select Ref Clk Enable REF IN Oscillator 100 MHz Oscillator This clock is user-selectable for either 156.25 MHz or 312.5 MHz. © National Instruments | 3-11...
  • Page 31 Chapter 3 Hardware Architecture NI-7935R The NI-7935R is an embedded FlexRIO controller with a LabVIEW Real-Time processor and reconfigurable FPGA. The NI-7935R includes a high-speed serial interface that uses Xilinx multi-gigabit transceiver (MGT) technology; you can reuse existing protocol IP that works with MGTs, or you can develop your own protocol IP.
  • Page 32 NI-793xR User Manual The following figure shows the NI-7935R LEDs in more detail. Figure 3-12. NI-7935R LEDs Power Status FPGA User RT User © National Instruments | 3-13...
  • Page 33 Chapter 3 Hardware Architecture The following figure shows the available signals on the NI-7935R adapter module connector. Figure 3-13. NI-7935R FPGA Connector Pinout Secondary Side Primary Side Secondary Side Primary Side +3.3V +3.3V S148 GPIO_CC_38_n S114 GPIO_CC_14_n TB_Power_Good S147 TB_Present_n GPIO_CC_38 S113 GPIO_CC_14...

  • Page 34: Ni-7935R Key Features

    NV Storage RT Clock Host VI Watch Dog Interrupts Controls/Indicators NI-Defined Bus TRIG Interfaces/Streaming IP REF IN LV FPGA VI User Defined SFP+ Socketed CLIP User Selected Adapter Adapter Module Module Memory CLIP Controller DRAM © National Instruments | 3-15...

  • Page 35: Clocking Architecture

    Chapter 3 Hardware Architecture Clocking Architecture The NI-7935R device includes dedicated clocking hardware to provide a flexible clocking solution for your FlexRIO system. Refer to Chapter 4, Developing with LabVIEW FPGA, for information about configuring clocks with LabVIEW FPGA. The NI-7935R clocking architecture includes the following clocks: •...
  • Page 36 Module IoModSyncClock Kintex-7 FPGA 10 MHz Reference Clock 40 MHz 100 MHz 156.25 MHz/ 200 MHz 312.5 MHz DRAM Clock Memory 166 MHz Controller Frequency Select Ref Clk Enable REF IN Oscillator 100 MHz Oscillator © National Instruments | 3-17...

  • Page 37: Developing With Labview Fpga

    Select the General category and check the Enable IO Module box. Select your adapter module from the IO Modules list, and select the CLIP you want to use from the Component Level IP box. Click OK. © National Instruments | 4-1...

  • Page 38: Adding Items To The Ni-793Xr Target

    Chapter 4 Developing with LabVIEW FPGA Adding Items to the NI-793xR Target You can add new or existing FPGA VIs, FPGA I/O items, FPGA FIFO, or FPGA clocks to the NI-793xR target in the Project Explorer window. You can also use folders to organize items under the FPGA target in the Project Explorer window.

  • Page 39: Auto-Loading Bitfiles On Power-Up

    VIs running on the FPGA target. After downloading and running the FPGA VI, keep LabVIEW open on the host computer to display and interact with the front panel window of the FPGA VI. © National Instruments | 4-3...

  • Page 40: Using The Ni Common Instrument Design Libraries

    Chapter 4 Developing with LabVIEW FPGA During interactive front panel communication, you cannot use LabVIEW debugging tools, including probes, execution highlighting, breakpoints, and single-stepping. To identify errors before you compile, download, and run the FPGA VI on the FPGA target, consider using a test bench.

  • Page 41: Basic Elements Overview

    At device power-up after the bitfile loads. • At the first time Run is called after a new bitfile is downloaded and the bitfile is not set to Run on Load. • When Run is called after Reset. © National Instruments | 4-5...

  • Page 42: Streaming

    Chapter 4 Developing with LabVIEW FPGA For more information about Run, Reset, and other Invoke methods, refer to the LabVIEW FPGA Module Help. When self-configuration executes, the clocking configuration enters an Note indeterminate state. When the clocking configuration is in an indeterminate state, you cannot rely on clocking stability from the clocking and routing hardware on the NI-793xR.

  • Page 43: Dma Streaming

    The number of array elements fed into the DMA FIFO from the Host can limit the maximum throughput for your application. Use large array subsets and set your FIFO depths to be deep enough to sustain high throughput. © National Instruments | 4-7...

  • Page 44: Simulating Fpga Behavior

    Chapter 4 Developing with LabVIEW FPGA Simulating FPGA Behavior You can simulate an FPGA VI that has been added to an NI-793xR target; however, you cannot open a reference to the simulated FPGA VI from the NI-793xR target. Instead, you must open a reference to the simulated FPGA VI by changing the application instance to My Computer.

  • Page 45: Programming The High-Speed Serial Ports

    Write custom protocol core IP If the sample project code is sufficient for your application, you do not have to modify the IP core, update the VHDL CLIP wrapper, or refresh the CLIP. © National Instruments | 5-1...

  • Page 46: Developing Mgt Socketed Clip

    Chapter 5 Programming the High-Speed Serial Ports Developing MGT Socketed CLIP This section provides steps for creating socketed CLIP for use with your application. Socketed CLIP provides the following functionality: • Allows you to insert HDL IP into an FPGA target, enabling VHDL code to communicate directly with an FPGA VI.

  • Page 47: Accessing The Xilinx Vivado Tools

    This error message is expected. You can ignore the error message if you are not using the Xilinx Embedded Development Kit (EDK). The EDK is not required for development with the NI-793xR. Click New Project and follow the instructions in the wizard. © National Instruments | 5-3...

  • Page 48: Generating An Ip Core From The Xilinx Vivado Ip Catalog

    Chapter 5 Programming the High-Speed Serial Ports Generating an IP Core from the Xilinx Vivado IP Catalog You may need to purchase and install additional licenses to generate some protocol IP core from Xilinx or third-party IP vendors. Refer to UG 973: Vivado Design Suite: Release Notes, Installation, and Licensing at for information about managing licenses.

  • Page 49: Building A Netlist From The Ip Core

    In the Tcl Console, enter to create the netlist write_edif <name of entity>.edf that you use when you import the IP core into your LabVIEW project. The netlist location is indicated by the Tcl Console window. © National Instruments | 5-5...
  • Page 50 Chapter 5 Programming the High-Speed Serial Ports The following figure shows the cells associated with the design in the Netlist window. To build files for an associated cell, enter the following command: .edf write_edif -cell <name of cell> <file name>.edf For example, to create an , enter the following command: .edf...

  • Page 51: Writing A Vhdl Wrapper Around The Protocol Ip Core

    CLIP if your protocol uses it directly. – The following is an example syntax for the constraint: create_clock -period <period in ns> [get_pins %ClipInstancePath%/<path to your clock pin relative to the top level CLIP VHDL>] © National Instruments | 5-7...

  • Page 52: Constraints And Hierarchy

    Chapter 5 Programming the High-Speed Serial Ports • If you generate an asynchronous reset within your CLIP VHDL, create a false path constraint from the register that generates the reset signal. Include a “don’t touch” attribute for any false path constraints. –...

  • Page 53: Documenting Your Ip

    LabVIEW on your host computer for a fully integrated development experience. Refer to the Related Documentation section of this manual for a list of LabVIEW FPGA documentation that you may find helpful as you develop your application. © National Instruments | 5-9...

  • Page 54: Configuring Mgt Socketed Clip In The Ni-793Xr Labview Fpga Targets

    Chapter 5 Programming the High-Speed Serial Ports Configuring MGT Socketed CLIP in the NI-793xR LabVIEW FPGA Targets Complete the following steps to configure MGT Socketed CLIP in your NI-793xR LabVIEW project: Create a new project by selecting File»New»Project, or open an existing project by selecting File»Open.

  • Page 55: Using Existing Vhdl Ip Inside Clip Or Ipin

    You can remove the enable chain under certain circumstances. Refer to Improving Timing Performance in Large Designs (FPGA Module) in the LabVIEW FPGA Module Help for more information about how to remove enable chains and when to do so. © National Instruments | 5-11...

  • Page 56: Programming With The Real-Time Target

    Device driver software—A software component that translates commands from LabVIEW into a format appropriate for a particular RT target and any installed I/O devices. You install the appropriate device driver software as a part of configuring your RT target. © National Instruments | 6-1...

  • Page 57: Installing And Configuring The Ni-793Xr

    Chapter 6 Programming with the Real-Time Target • Host computer—The computer you use to design a real-time application. You deploy a real-time application from the host computer to the RT target. You can also communicate with the RT target through a user interface running on the host computer. •...

  • Page 58: Real-Time System Integration

    System Resources::Fans FlexRIO::System Resources::FanPWM property. The speed reading property is in units of RPM, and the PWM property is in units of percentage. © National Instruments | 6-3...

  • Page 59: Power/Thermal Protection And Shutdown

    Chapter 6 Programming with the Real-Time Target To query the CPU Temp x and FPGA Temp sensors, filter for the resource and query system the properties under the category. System Resources::Temperature Sensors Figure 6-1. Querying Fan and CPU Temperatures You can also monitor the FPGA Temp sensor on the RIO0 resource. To do this, filter for the resource and query the property.

  • Page 60: Communicating With Applications On An Rt Target

    RT target. However, front panel communication is not deterministic and can affect the determinism of a time-critical VI. Use network communication methods to increase the efficiency of the communication between a host computer and VIs running on the RT target. © National Instruments | 6-5...

  • Page 61: Network Communication

    Chapter 6 Programming with the Real-Time Target Network Communication With network communication, a host VI runs on the host computer and communicates with the VI running on the RT target using specific network communication methods such as TCP, VI Server, and in the case of non-networked RT Series plug-in devices, shared memory reads and writes.

  • Page 62: Labview Real-Time Module Release And Upgrade Notes

    The LabVIEW Real-Time Module Release and Upgrade Notes contains information to help you install and configure the Real-Time Module and a list of upgrade issues and new features. Complete the following steps to access this document: Open the directory. labview\manuals Double-click to open this manual. RT_Release_Upgrade_Notes.pdf © National Instruments | 6-7...
  • Page 63 SocketClk40 Clock A 40 MHz clock that runs continuously regardless of connectivity. This signal is connected to the 40 MHz Onboard Clock signal, which is the default top-level clock for the LabVIEW FPGA VI. © National Instruments | A-1...
  • Page 64 Appendix A CLIP Signals Table A-1. NI-7932R CLIP Signals (Continued) Port Direction Clock Domain Description aResetSl Async This signal is not required. This signal is an asynchronous reset signal from the LabVIEW FPGA environment. If you create an input signal to your CLIP and assign it as Reset in the CLIP wizard, that signal is driven as an asynchronous reset...
  • Page 65 This signal is also called MODDEF2. Port<0..1>_ Async Unique 48-bit MAC address MacAddress assigned to Port<0..1>. Use this address when implementing a network interface controller on Port<0..1>. Port<0..1>_ Async When asserted, this signal MacAddressValid indicates that Port<0..1>_MacAddress is valid. © National Instruments | A-3...
  • Page 66 Appendix A CLIP Signals Table A-1. NI-7932R CLIP Signals (Continued) Port Direction Clock Domain Description sPort<0..1>_ SocketClk40 Enables or disables the power EnablePower supply to Port <0..1>. This signal is active high. sPort<0..1>_ SocketClk40 Indicates that the power supply PowerGood to the cable for Port <0..1>...
  • Page 67 Low indicates normal operation. Port<0..1>_ABS Async When high, this input indicates that a module is plugged into the SFP+ socket. Low indicates that a module has been detected. © National Instruments | A-5...
  • Page 68 Appendix A CLIP Signals Table A-2. NI-7935R CLIP Signals (Continued) Port Direction Clock Domain Description Port<0..1>_Tx_ Async When high, this output shuts Disable down the transmitter optical transmitter. When low, operation is enabled. Port<0..1>_Rs<0..1> Async Rate selection pins. Port<0..1>_SCL In/Out Async Bidirectional serial clock signal for the two-wire communication...
  • Page 69 Port <0..1>. This signal is active high. sPort<0..1>_ SocketClk40 Indicates that the power supply PowerGood to the cable for Port <0..1> is enabled. This signal may deassert if an over-power condition is detected. © National Instruments | A-7...
  • Page 70 70,000 h (40 °C) Refer to the Sanyo Denki website for complete specifications. Replacing the Fan The NI-793xR includes a replaceable fan assembly. For fan troubleshooting information and to order replacement parts , refer to ni.com/support © National Instruments | B-1...
  • Page 71 NI Services National Instruments provides global services and support as part of our commitment to your success. Take advantage of product services in addition to training and certification programs that meet your needs during each phase of the application life cycle; from planning and development through deployment and ongoing maintenance.
  • Page 72 Appendix C NI Services • Training and Certification—The NI training and certification program is the most effective way to increase application development proficiency and productivity. Visit for more information. ni.com/training – The Skills Guide assists you in identifying the proficiency requirements of your current application and gives you options for obtaining those skills consistent with your time and budget constraints and personal learning preferences.
  • Page 73 NI-793xR modules use Xilinx Kintex-7 FPGAs. GPIO General-purpose input/output Hardware-description language. Language that describes a circuit’s operation, design, and organization. LVFPGA LabVIEW FPGA Multi-gigabit transceiver. An MGT is a SerDes capable of operating at serial bits above 1 Gb/s. © National Instruments | G-1...
  • Page 74 Glossary Programmable function interface SCTL Single cycle timed loop SFP+ Enhanced small form-factor pluggable VHDL VHSIC Hardware Description Language G-2 | ni.com...

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