XMOS VocalFusion XVF3510 User Manual page 43

The SPI master peripheral supports the following fixed specifications:
-
Single chip select line
-
1Mbps fixed clock speed
-
Supports either reads or writes. Duplex read/writes are not supported.
-
Most significant bit transferred first
-
Mode 0 transfer (CPOL = 0, CPHA = 0)
NOTE: The chip select is asserted a minimum of before 20ns the start of the transfer and de-asserted
a minimum of 20ns after the transfer ends.
The SPI Master is controlled using the following commands.
Table 4-7 SPI peripheral interface commands
COMMAND
GET_SPI
GET_SPI_READ_HEADER
SET_SPI_PUSH
SET_SPI_PUSH_AND_EXEC uint8
SET_SPI_READ_HEADER
Reads of up to 56 Bytes at a time may be performed but writes of 128 Bytes at a time can be made by
pushing multiple commands into a command stack and executing them in one go. The transaction is
performed within a single chip select assertion.
XM-014232-PC
TYPE DIR ARGS DESCRIPTION
uint8 READ 56 Gets the contents of the SPI read buffer.
uint8 READ 2 Get the address and count of next SPI read.
uint8 WRITE 56 Push SPI command data onto the execution queue.
Push SPI command data and execute the command from the
WRITE 56
stack. Data will then be sent to SPI device.
uint8 WRITE 2 Set address and count of next SPI read.
Figure 4-7 SPI peripheral, read sequence
Figure 4-8 SPI peripheral, write sequence
43