Lanner electronics IAC-F695 Series Manual page 34

Picmg full-size cpu card for amd socket a processor
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AWARD BIOS SETUP
SDRAM Cycle Length : This item allows you to select the SDRAM cycle length. The
settings are 2 or 3.
Bank Interleave: If you set this item to Enable, BIOS will set the bank interleave in 2 way
or 4 way based on the configuration of SPD EPROM
Memory Hole : In order to improve performance, certain space in memory can be
reserved for ISA cards. This memory must be mapped into the memory space below
16MB.
Enabled
Disabled (default)
PCI Master Pipeline Req: Enable this item to enhance PCI bus for better performance.
P2C / C2P Concurrency : This item allows you to Enable or Disable the PCI to CPU,
CPU to PCI concurrency. The default setting is "Enabled".
Fast R-W Turn Around: This item controls the DRAM timing. It allows the user to Enable
or Disable the fast read, write turn around. The settings are Enabled or Disabled. The
default setting is Disabled.
System BIOS Cacheable : Selecting "Enabled" allows caching of the system BIOS ROM
at F0000h – FFFFFh, resulting in better system performance. However, if any program
writes to this memory area, a system error may result. The settings are "Enabled" and
"Disabled".
Video RAM Cacheable : Select "Enabled" allows caching of the video BIOS, resulting in
better system performance. However, if any program writes to this memory area, a
system error may result. The settings are: "Enabled" and "Disabled".
Power-Supply Type: Select the power supply type. The default setting is "AT".
OnChip USB : Set this option to "Enabled" or "Disabled" the onchip USB controller. The
default setting is "Disabled".
Memory hole supported
Memory hole not supported
~30~

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