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3.5 C
HIPSET
When you select the "CHIPSET FEATURES SETUP" on the main program, the screen
display will appears as:
Chipset Features Setup Screen
CMOS Setup Utility – Copyright © 1984-2001 Award Software
DRAM Timing By SPD
X
DRAM Clock
X
SDRAM Cycle Length
X
Bank Interleave
Memory Hole
PCI Master Pipeline Req
P2C/C2P Concurrency
Fast R-W Turn Around
System BIOS Cacheable
Video RAM Cacheable
Power-Supply Type
OnChip USB
USB Keyboard Support
CPU to PCI Write Buffer
PCI Dynamic Bursting
PCI Master 0 WS Write
PCI Delay Transaction
PCI#2 Access #1 Retry
á â à Move Enter: Select
F5: Previous Values F6: Fail-Safe Defaults
DRAM Timing By SPD: This sets the optimal timings of SDRAM by reading the contents
in the SPD device. The EEPROM on the memory module stores critical parameter
information about the module, such as memory type, size, speed, voltage interface, and
module banks.
DRAM Clock : The chipset support synchronous and asynchronous mode between the
host clock and DIMM clock.
Host CLK (default)
100MHz
133MHz
F
S
EATURES
ETUP
Advanced Chipset Features
Enabled
133MHz
3
Disabled
Disabled
Enabled
Enabled
Disabled
Disabled
Disabled
AT
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
+/-/PU/PD: Value
DIMM clock equal to host clock
DIMM clock equal to 100MHz
DIMM clock equal to 133MHz
F10: Save Esc: Exit F1: General Help
F7: Optimized Default
~ 29 ~
AWARD BIOS SETUP
Item Help
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