Table of Contents
Advertisement
Table 12: Parameter of WLAN_SLP_CLK
Parameter
Comments
t(xoh)
Sleep-clock logic high
t(xol)
Sleep-clock logic low
T
Sleep-clock period
Sleep-clock frequency
F
(F = 1/T)
Vpp
Peak-to-peak voltage
3.7.2.
SW_CTRL*
SW_CTRL can be used to control external VDD_RF power supply chip. The following table shows the pin
definition of SW_CTRL.
Table 13: Pin Definition of SW_CTRL
Pin Name
Pin No.
SW_CTRL
23
3.8. RF Antenna Interfaces
This information will be included in future revisions of this document.
FC64E_Hardware_Design
Figure 10: Requirements of WLAN_SLP_CLK
I/O
Description
DO
VDD_RF control
Wi-Fi&Bluetooth Module Series
Min
Typ
4.58
4.58
4.58
4.58
30.5208
32.7645
1.8
Comment
1.8 V power domain.
Active high.
If unused, keep this pin open.
Max
Unit
25.94
μs
25.94
μs
μs
kHz
V
31 / 53
Advertisement
Table of Contents
