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Summary of Contents for NXP Semiconductors UM11650
- Page 1 UM11650 KIT-TPLSNIFEVB tool Rev. 2 — 23 June 2023 User manual Document information Information Content Keywords TPL, ETPL, electrical transport protocol link, decoder, TPL sniffer Abstract This document helps users understand how to use the KIT-TPLSNIFEVB to acquire ETPL communications.
- Page 2 UM11650 NXP Semiconductors KIT-TPLSNIFEVB tool Revision history Date Description 20230623 • Updated vocabulary throughout the document • Updated mentions of software decoder available throughout the document 20210804 initial version IMPORTANT NOTICE For engineering development or evaluation purposes only NXP provides the product under the following conditions: This evaluation kit is for use of ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY.
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Page 3: Introduction
UM11650 NXP Semiconductors KIT-TPLSNIFEVB tool 1 Introduction The KIT-TPLSNIFEVB, also called transport protocol link (TPL) sniffer is working with a logic analyzer (preferably a Saleae logic analyzer) and its software to help analyze electrical transport protocol link (ETPL) signals. Figure 1. KIT-TPLSNIFEVB Placed in any ETPL bus, it non-intrusively listens to all messages and monitors the frame traffic on the bus (the TPL sniffer works in listen mode only). -
Page 4: Finding Kit Resources And Information On The Nxp Website
CE marked unless assessed. 2 Finding kit resources and information on the NXP website NXP Semiconductors provides online resources for this tool and its supported devices on website. The information page for the KIT-TPLSNIFEVB tool provides overview information, documentation, software and tools, parametrics, ordering information and a Getting Started tab. -
Page 5: Getting Ready
UM11650 NXP Semiconductors KIT-TPLSNIFEVB tool 3 Getting ready 3.1 Kit contents • Assembled and tested TPL sniffer dongle in anti-static bag • A logic analyzer connection cable with 8-pin headers • An ETPL bus connection twisted cable with 2-pin headers Figure 3. Kit contents... -
Page 6: Block Diagram
UM11650 NXP Semiconductors KIT-TPLSNIFEVB tool 4.2 Block diagram TPL frames are received and sent in SPI The TPL sniffer interfaces the TPL bus format by the MC33664 and buffered by the with transformer isolation cable driver CABLE TPL_IN MC33664 DRIVER... -
Page 7: Optional Etpl Bus Loading
UM11650 NXP Semiconductors KIT-TPLSNIFEVB tool Note: The two ETPL interface connectors are named J1 and J2 in the schematic diagram. Figure 5. ETPL bus connectors 5.1.1 Optional ETPL bus loading The TPL sniffer is designed to add minimal load to the ETPL bus by default. Therefore, it does not add any termination impedance and the differential load seen from the bus is that of an input impedance of the MC33664 reflected on the high-voltage side by the 1 : 1 ratio T1 isolation transformer. -
Page 8: Connecting To The Logic Analyzer
UM11650 NXP Semiconductors KIT-TPLSNIFEVB tool Figure 6. Power and data connectors 5.2.1 Connecting to the logic analyzer The data output connector (J3) is an 8-pin 4 × 2 male connector used as an interface to the logic analyzer, to transfer TPL messages converted to SPI format. -
Page 9: Interfacing With The Saleae Logic Analyzer
UM11650 NXP Semiconductors KIT-TPLSNIFEVB tool Table 1. Analyzer connector (J3) pin assignment Signal Description INTB SPI interrupt signal ground RXCLK SPI bus clock ground RXDATA SPI bus data ground RXCSB SPI chip select ground Figure 7. Analyzer connector pinout The supplied 8-pin connection cable should be plugged into the ANALYZER connector with the blue wires on top (NXP logo side) and the black wires on the bottom. -
Page 10: Powering The Tpl Sniffer
UM11650 NXP Semiconductors KIT-TPLSNIFEVB tool Figure 8. Saleae logic analyzer Saleae provides a software interface with its product to help decode the acquired signals. To learn more, visit Saleae website. Plug-ins and extensions for the Saleae logic analyzer software are available to decode TPL frames. Visit http:// www.nxp.com/KIT-TPLSNIFEVB... -
Page 11: References
UM11650 NXP Semiconductors KIT-TPLSNIFEVB tool Table 3. Environmental characteristics Description Value Operating temperature 0 °C to 40 °C Storage temperature −40 °C to +70 °C Humidity 5 % to 95 % relative humidity, non-condensing Table 4. Mechanical characteristics Description Value Enclosure dimensions 72 mm W ×... -
Page 12: Legal Information
NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, Evaluation products — This product is provided on an “as is” and “with all punitive, special or consequential damages (including - without limitation - faults”... - Page 13 UM11650 NXP Semiconductors KIT-TPLSNIFEVB tool NXP — wordmark and logo are trademarks of NXP B.V. 8.3 Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. UM11650 All information provided in this document is subject to legal disclaimers.
- Page 14 UM11650 NXP Semiconductors KIT-TPLSNIFEVB tool Tables Tab. 1. Analyzer connector (J3) pin assignment ... 9 Tab. 3. Environmental characteristics ......11 Tab. 2. Electrical characteristics ........10 Tab. 4. Mechanical characteristics ......11 Figures Fig. 1. KIT-TPLSNIFEVB ..........3 Fig. 5. ETPL bus connectors ........7 Fig.
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Page 15: Table Of Contents
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2023 NXP B.V. All rights reserved. For more information, please visit: http://www.nxp.com Date of release: 23 June 2023 Document identifier: UM11650...
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