System Control Block Diagram - JVC HR-J692US Service Manual

SYSTEM CONTROL BLOCK DIAGRAM

DRUM MOTOR
5 8 0
M
1 2
1 2
CN3001
CAP.M FG
5 7
1 1
CAP.M F/R
4 4
3 in 1 MDA
CAP.M VCTL
9 9
CAP MOTOR
LM F/R/S
10 10
DRUM PG/FG
11 11
M
DRUM CTL
12 12
5 5 LOADING MOTOR
M
JS3001
ROTARY
LSD
5
ENCODER
LSC
4
LSB
3
LSA
2
1 2
A/C HEAD
A/C HEAD CN2001
CN1
CTL HEAD ( - )
2 5
CTL CTL HEAD ( + )
1 6
I2C DATA A/V
I2C CLK A/V
TO
D.FF
VIDEO/AUDIO
V. PULSE
VIDEO ENV
TO
VIDEO/AUDIO V TO OSD
TO
V FROM OSD
TERMINAL
Note : For the waveforms in this block diagram, refer to page 2-22.
MAIN ( SYSCON )
3
WF1
WF2
PC3001
PHOTO
SENSOR PC3002
PHOTO
SENSOR
WF3
LPF
VIDEO SECTION ( ON SCREEN )
IC3001
( SYSTEM CONTROL MICRO PROCESSOR )
84
SW_PT_ADJ
37
X OUT
68
CAP.M FG
62
CAP.M F/R
38
33
X IN
CAP.M VCTL
61
LM F/R/S
65
DRUM PG/FG
34
DRUM VCTL
22
REC SAFETY
78
END SENSOR
25
RESET
1
SP FG
2
TU FG
60
94 MODEL_OPTION_1
LSD
93
63
LSC
MODEL_OPTION_2
92
LSB 64
91
MODEL_OPTION_3
LSA
TP4001
CTL. P
31
76
I2C DATA
CTL AMP OUT
32
I2C CLK/TEST
75
CTL -
74
CTL +
WF4
( SERIAL MEMORY )
17
I2C DATA A/V
18
I2C CLK A/V
23
D.FF
24
V. PULSE
83
VIDEO ENV
50 28
H.REC_ST ( H )
SYN IN
35
A.MUTE ( H )
27
N.REC ST ( H )
49
V_TO_OSD 15
N.REC ( H )
WF5
47
VIDEO_OSD_OUT
WF6
2-25 2-26
VR4028
SWITCHING POINT ADJ.
X3001
MAIN SYSTEM
CLOCK
( 14.32MHz )
+5V
S3001 REC SAFETY SW
END
Q3002
SENSOR
D3005
1 2
RESET AL5.8V SYS
Q3006 , Q3007
4
( RESET )
6
SCL
5
SDA
IC3004
OPEN
TO TUNER
I2C DATA
I2C CLK
TO FMA/DEMOD
I2C DATA
I2C CLK
H.REC_ST(H)
A.MUTE ( H )
A.MUTE ( H )
TO
N.REC ST ( H )
VIDEO/AUDIO
N.REC ( H )