System Control Block Diagram - JVC HR-S5950EU Service Manual

4.21

SYSTEM CONTROL BLOCK DIAGRAM

DRUM MOTOR
5 8
M
5
1 2
1 2
CAP.M FG
5 7
1
CAP.M F/R
4 4
3 in 1 MDA
CAP.M VCTL
9
CAP MOTOR
LM F/R/S
10 10
DRUM PG/FG
11
4
M
DRUM CTL
12 12
5 5 LOADING MOTOR
M
3
ROTARY
LSA
ENCODER LSB
3
LSC
LSD
5
1 2
A/C HEAD
A/C HEAD CN2001
CN1
CTL HEAD ( - )
2
CTL
CTL HEAD (+)
1
2
NORM/MESEC/S
D.FF
TO V. PULSE
VIDEO/N. AUDIO VIDEO_ENV
SECAM_DET
SECAM(H)
TO TERMINAL Y.OUT(H)
TO
VIDEO/N. AUDIO
V TO OSD
TO
V FROM OSD
TERMINAL
1
A
MAIN ( SYSCON, VPS/PDC SLICER )
0 3
WF1
CN3001
1
9
11
WF2
PC3001
PHOTO
SENSOR
PC3002
PHOTO
SENSOR
JS3001
2
4
5
6
ONLY USED FOR
EU/MS MODEL
VIDEO SECTION ( ON SCREEN )
Note : For the waveforms in this block diagram, refer to page 4-33.
B C
IC3001
( SYSTEM CONTROL MICRO PROCESSOR )
OSC2(OUT)
OSC1(IN)
X1
X2
9
CFG
55
CAP_REV(H)
108
CAP_CTL_V
44
REC_SAFETY
LM_FR(LMC1)
104
DFG
107
DRUM_CTL_V
END_SENSOR
CH+A
CH+B
PAL_PB ( H )
H.REC_ST ( H )
37 I2C_DATA
SP FG
I2C_CLK
42 A.MUTE ( H )
TU FG
N.REC ST ( H )
N.REC ( H )
FULL_E_ON(H)
67
LSA
38
LSB
34
LSC
33
LSD
TP4001
CTL. P
I2C_DATA2
WF3
7
CTL_AMP_OUT
I2C_CLK2
SYNC_DET(H)
4
CTL(-)
3
CTL(+)
WF4
35
NORM/MESEC/S
105
D.FF
109
V. PULSE
26
S. CASS(H)/JSA
VIDEO_ENV
43
SECAM_DET JSB
89
SECAM(H)
97
Y.OUT(H)
16
CVIN2
SAT_CTL
17
CVIN1
R. PAUSE
WF5
19
CVOUT
WF6
D E
4-35 4-36
80
X3002
MAIN SYSTEM
CLOCK
78
(10MHz)
76
ONLY USED FOR
X3001
EU MODEL
C3025
TIMER CLOCK
TIMER CLOCK
( 32kHz )
75
+5V
S3001 REC SAFETY SW
39
31
END
Q3003
SENSOR
83
87
95
93
62
61
94
100
101
96
IC3003
( SERIAL MEMORY )
IC251
6
(VPS/PDC SLICER)
SCL
5
SDA 16
SYN_IN
2
XTAL_IN
60 6
SDA
7
59
SCL
86 8
SYNC_JDG
40
NOT USED
41
53
NOT USED
99
F
CTL3(CH+A)
TO
CH+B TERMINAL
I2C_DATA
I2C_CLK
TO
A.MUTE ( H )
FMA
PAL_PB(H)
H.REC_ST(H)
I2C_DATA
I2C_CLK
A.MUTE ( H )
N.REC_ST(H)
TO
N.REC ( H ) VIDEO/N. AUDIO
CTL5(FULL_E_ON ( H ))
V_TO_VPS/PDC
2Fsc
I2C_CLK2 TO
I2C_DATA2 TUNER
G H