System Control Block Diagram - JVC HR-S6950EU Service Manual

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4.27

SYSTEM CONTROL BLOCK DIAGRAM

5
DRUM MOTOR
5 8
M
1 2
1 2
5 7
1
4
4 3 in 1 MDA
9
CAP MOTOR
10
11
M
12
5 5 LOADING MOTOR
M
3
ROTARY
ENCODER
1 2
A/C HEAD
A/C HEAD
CN1
2
CTL CTL
2
1
TO
VIDEO/N. AUDIO
1
A
MAIN ( SYSCON, MAIN TERMINAL )
0 3
WF1
CN3001
CAP.M_FG
1
CAP.M_F/R
4
CAP.M_VCTL
9
LM_F/R/S
10
DRUM_PG/FG
11
DRUM_VCTL
12
WF2
PC3001
PHOTO
SENSOR
PC3002
PHOTO
SENSOR
JS3001
LSA
2
LSB
3
LSC
4
LSD
5
CN2001
CTL HEAD ( - )
5
HEAD (+)
6
NORM/MESEC/S
D.FF
V. PULSE
VIDEO_ENV
C.SYNC
SECAM_DET
SECAM(H)
Note : For the waveforms in this block diagram, refer to page 4-39.
B C
IC3001
( SYSTEM CONTROL MICRO PROCESSOR )
OSC2(OUT)
OSC1(IN)
X1
X2
8
CFG
28
CAP.M F/R
101
CAPPWM
35
LM_F/R/S REC_SAFETY
108
DFG
102
DRUMPWM
S.CASS(H)
START_SENSOR
END_SENSOR
PAL_PB ( H )
H.REC_ST ( H )
54 I2C_DATA
SP FG
I2C_CLK
55 A.MUTE ( H )
TU FG
N.REC ST ( H )
N.REC ( H )
FULL_E_ON(H)
25
LSA
26
LSB
27
LSC
36
LSD
TP4001
CTL. P
WF3
I2C_DATA2
6
CTLAMPOUT
I2C_CLK2
3
SYNC_DET(H)
CTL(-)
1
CTL(+)
WF4
JSA
11
NORM/MESEC/S JSB
100
V.FF
110
V. PULSE
13
VIDEO_ENV
98
C.SYNC
SECAM_DET
12
SECAM(H)
77
WF5
SAT_CTL
R. PAUSE
Digitized in Heiloo Netherland
D
4-45 4-46
69
X3002
MAIN SYSTEM
CLOCK
67
(10MHz)
65
ONLY USED FOR
X3001
HR-S6950EU/S7950EU/S7955EK
C3025
TIMER CLOCK
TIMER CLOCK
( 32kHz )
64
+5V
S3001 REC SAFETY SW
58
S3002 S.CASS SW
46
14 START
Q3002
SENSOR
15 END
Q3003
SENSOR
79
88
49
50
74
90
105
104
IC3003
( SERIAL MEMORY )
6
SCL
5
SDA
76
75
72
CN7001
56
3
57
5
CN7005 CN7002
1 4
3 2
ONLY USED FOR
2 8 MINI FRONT
HR-S7955MS
CN904 CN914
Q7201
44 3
BUF
1
2
32
2 1
3
2
1
TERMINAL(I/O)
0 6
ONLY USED FOR
HR-S7955MS/S7950EU/S7955EK
E F
3/28/2017
I2C_DATA_A/V
I2C_CLK_A/V
TO
A.MUTE ( H )
FMA
PAL_PB(H)
H.REC_ST(H)
I2C_DATA_A/V
I2C_CLK_A/V
A.MUTE ( H )
TO
N.REC_ST(H) VIDEO/N. AUDIO
N.REC ( H )
FULL_E_ON ( H )
I2C_DATA2
TO
TUNER
I2C_CLK2
TO TERMINAL(S-SUB)
CN901 CN911
2 I2C_DATA
I2C_CLK
1
I2C_DATA2
TO
I2C_CLK2
ON SCREEN
SYNC_DET(H)
CN7003
4
4
6
UN7001
2
ADV. JOG
3 8
J921
SAT.CTL
J922
R.PAUSE
G H