ON Semiconductor MT9V117PACSTCH-GEVB User Manual

ON Semiconductor MT9V117PACSTCH-GEVB User Manual

Mt9v117 evaluation board

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MT9V117PACSTCH-GEVB
MT9V117 Evaluation Board
User's Manual

Evaluation Board Overview

The evaluation boards are designed to demonstrate the features of
ON Semiconductor's image sensors products. This headboard is
intended to plug directly into the Demo 2X system. Test points and
jumpers on the board provide access to clock, I/Os and other
miscellaneous signals.

Features

Clock Input
Default − 54 MHz crystal oscillator
Optional Demo 2X controlled MClk
Two Wire Serial Interface
Selectable base address
Parallel Interface
ROHS Compliant

Block Diagram

JTAG_RST_L
ON Semi
Demo 2
Reset
Supervisor
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 0
+1.8 V +2.8 V/+1.8 V
D_RST_L
SYSRST_L
AND
RESET_N
Gate
RST_L
+1.8 V
STANDBY
MT9T117
JTAG
JTAG
JTAG
+2.8 V
SADDR
SAADR
CLK
OSC
CLKN
+3.3 V
+2.8 V/+1.8 V
+1.8 V
Figure 2. Block Diagram of MT9V117PACSTCH−GEVB
EVAL BOARD USER'S MANUAL
Figure 1. MT9V117 Evaluation Board
IMG_OUT
DOUT
ON Semiconductor
LSB[1:0]
I2C
ON Semi Demo 2
I2C
Power
+5.0 V
Supply
1
www.onsemi.com
Demo 2
RS232
RJ11
Publication Order Number:
EVBUM2467/D

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Summary of Contents for ON Semiconductor MT9V117PACSTCH-GEVB

  • Page 1 Evaluation Board Overview The evaluation boards are designed to demonstrate the features of www.onsemi.com ON Semiconductor’s image sensors products. This headboard is intended to plug directly into the Demo 2X system. Test points and EVAL BOARD USER’S MANUAL jumpers on the board provide access to clock, I/Os and other miscellaneous signals.
  • Page 2 MT9V117PACSTCH−GEVB Top View RESET Switch SW1 Parallel O/P P6 UART Control JP9 ATEST JP8 Configuration Switch SW2 CLK_SELECT JP7 EEPROM ADDR SW3 +VAAPIX JP2 ON_LED JP6 +1V8_VDD JP3 +VDDIO_SEL JP4 +VDDIO JP5 +2V8_VAA JP1 Figure 3. Top View of Evaluation Board − Default Jumpers Bottom View Baseboard Connector P2 Figure 4.
  • Page 3 MT9V117PACSTCH−GEVB Jumper Pin Locations The jumpers on headboards start with Pin 1 on the leftmost side of the pin. Grouped jumpers increase in pin size with each jumper added. Pin 1 Pins 1−4 Figure 5. Pin Locations for a Single Jumper. Pin 1 is Located at the Leftmost Side and Increases as it Moves to the Right Pin 1 Pins 1 and 2...
  • Page 4 A0 ON, A1 ON, EEPROM Address set to 0xA0 A2 ON, WP ON Interfacing to ON Semiconductor Demo 2X Baseboard The ON Semiconductor Demo 2X baseboard has headboard. The four mounting holes secure the baseboard a similar 26-pin connector which mates with P2 of the and the headboard with spacers and screws.
  • Page 5 LIMITATIONS OF LIABILITY: ON Semiconductor shall not be liable for any special, consequential, incidental, indirect or punitive damages, including, but not limited to the costs of requalification, delay, loss of profits or goodwill, arising out of or in connection with the board, even if ON Semiconductor is advised of the possibility of such damages. In no event shall ON Semiconductor’s aggregate liability from any obligation arising out of or in connection with the board, under any theory of liability, exceed the purchase price paid for the board, if any.

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