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3.2.1.8 LVDS Flat Panel signals
The SoCs offer two multi-purpose Digital Display Interfaces, which allow the implementation of HDMI/DVI, Display Port (DP) or embedded Display Port (eDP), and a
dedicated eDP interface.
The LVDS interface, which is frequently used in many application fields, is not directly supported by the SOC.
For this reason, considering that LVDS interface can be multiplexed on the same pin with the eDP interface, on the board can be implemented an eDP to LVDS
bridge (NXP PTN3460), which allow the implementation of a Dual Channel LVDS, with a maximum supported resolution of 1920x1200 @ 60Hx (dual channel mode).
Such an interface is derived from the SOCs' dedicated eDP Interface.
Please remember that LVDS interface is not native for this Intel
the factory option purchased, on the same pins it is possible to have available LVDS or eDP interface.
Please take care of specifying if it is necessary LVDS interface or eDP, before placing an order of this product.
Here following the signals related to LVDS management:
LVDS_A0+/LVDS_A0-: LVDS Primary Channel #0 differential data pair #0.
LVDS_A1+/LVDS_A1-: LVDS Primary Channel #0 differential data pair #1.
LVDS_A2+/LVDS_A2-: LVDS Primary Channel #0 differential data pair #2.
LVDS_A3+/LVDS_A3-: LVDS Primary Channel #0 differential data pair #3.
LVDS_A_CLK+/LVDS_A_CLK-: LVDS Primary Channel #0 differential clock.
LVDS_B0+/LVDS_B0-: LVDS Secondary Channel #0 differential data pair #0.
LVDS_B1+/LVDS_B1-: LVDS Secondary Channel #0 differential data pair #1.
LVDS_B2+/LVDS_B2-: LVDS Secondary Channel #0 differential data pair #2.
LVDS_B3+/LVDS_B3-: LVDS Secondary Channel #0 differential data pair #3.
LVDS_B_CLK+/LVDS_B_CLK-: LVDS Secondary Channel differential Clock
LVDS_PPEN: +3.3V_S electrical level Output, Panel Power Enable signal. It can be used to turn On/Off the connected LVDS display.
LVDS_BLEN: +3.3V_S electrical level Output, Panel Backlight Enable signal. It can be used to turn On/Off the backlight's lamps of connected LVDS display.
LVDS_BLT_CTRL: this signal can be used to adjust the panel backlight brightness in displays supporting Pulse Width Modulated (PWM) regulations.
LVDS_DID_DAT: DisplayID DDC Data line for LVDS flat Panel detection. Bidirectional signal, electrical level +3.3V_S with a 2k2Ω pull-up resistor.
LVDS_DID_CLK: DisplayID DDC Clock line for LVDS flat Panel detection. Bidirectional signal, electrical level +3.3V_S with a 2k2Ω pull-up resistor.
ATLAS
ATLAS User Manual - Rev. First Edition: 1.0 - Last Edition: 1.2 - Author: S.O. - Reviewed by C.M. Copyright © 2023 SECO S.r.l.
®
family of SOCs, it is derived from an optional eDP-to-LVDS bridge. Depending on
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