N.a; Pwr - Seco Qseven ATLAS User Manual

N.A.

N.A.
N.A.

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3.2.1.1 PCI Express interface signals
The board can offer externally four PCI Express lane, which are directly managed by the SOCs.
PCI express Gen 2.0 (5Gbps) is supported.
Here following the signals involved in PCI express management
PCIE0_TX+/PCIE0_TX-: PCI Express lane #0, Transmitting Output Differential pair
PCIE0_RX+/PCIE0_RX-: PCI Express lane #0, Receiving Input Differential pair
PCIE1_TX+/PCIE1_TX-: PCI Express lane #1, Transmitting Output Differential pair
PCIE1_RX+/PCIE1_RX-: PCI Express lane #1, Receiving Input Differential pair
PCIE2_TX+/PCIE2_TX-: PCI Express lane #2, Transmitting Output Differential pair
PCIE2_RX+/PCIE2_RX-: PCI Express lane #2, Receiving Input Differential pair
PCIE3_TX+/PCIE3_TX-: PCI Express lane #3, Transmitting Output Differential pair
PCIE3_RX+/PCIE3_RX-: PCI Express lane #3, Receiving Input Differential pair
PCIE_CLK_REF+/ PCIE_CLK_REF-: PCI Express Reference Clock, Differential Pair. Please consider that only one reference clock is supplied, while there are four
different PCI express lanes. When more than one PCI Express lane is used on the carrier board, then a zero-delay buffer must be used to replicate the reference
clock to all the devices.
®
PCIE_WAKE#: Qseven Module's Wake Input, +3.3V_S voltage, with 10kΩ pull-up resistor;it must be externally driven by devices requiring waking up the system.
On the carrier board, connect it directly to the PCI-e/miniPCI-e connector's WAKE# signal, or to WAKE# signal of any eventual PCI-e Controller present on the Carrier
Board.
ATLAS
ATLAS User Manual - Rev. First Edition: 1.0 - Last Edition: 1.2 - Author: S.O. - Reviewed by C.M. Copyright © 2023 SECO S.r.l.
N.C.
N.C.
N.C.
+5V_S
+5V_S
+5V_S
+5V_S
+5V_S
+5V_S
213 214 N.C.
215 216 N.C.
217 218 N.C.
219 220 +5V_S
221 222 +5V_S
223 224 +5V_S
225 226 +5V_S
227 228 +5V_S
229 230 +5V_S
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