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Schematic Diagram (TMDS receiver)
B_B0
B_B1
B_B2
51
QO2
B_B3
52
QO3
B_B4
53
QO4
B_B5
54
QO5
B_B6
55
QO6
B_B7
56
QO7
57
OVCC
58
OGND
G_B0
2504
59
QO8
G_B1
470P/0805
60
QO9
G_B2
61
QO10
G_B3
62
QO11
G_B4
63
QO12
G_B5
64
QO13
G_B6
65
QO14
G_B7
66
QO15
67
VCC
68
GND
R_B0
2505
69
QO16
R_B1
470P/0805
70
QO17
R_B2
71
QO18
R_B3
72
QO19
R_B4
73
QO20
R_B5
74
QO21
R_B6
75
QO22
R_B7
5501
DIGITAL 3V3
+3.3V
BLM31P500S
RXB+
RXB-
2513
RXG+
10U/1206
RXG-
RXR+
RXR-
RXC+
RXC-
(FROM MCU)
Digital Low
Analog High
SI_PDN
(SI_PDN, POWER-ON state
is HIGH)
Back
3501
47R/PM5/0805
3502
47R/PM5/0805
3503
0R/PM5/0805
3504
0R/PM5/0805
R_A7
R_A6
R_A5
R_A4
R_A3
R_A2
R_A1
R_A0
G_A7
G_A6
7501
25
G_A5
QE13
24
G_A4
QE12
23
G_A3
QE11
22
G_A2
QE10
21
G_A1
QE9
20
G_A0
2515
470P/0805
QE8
19
OGND
18
OVCC
17
B_A7
QE7
16
B_A6
QE6
15
B_A5
QE5
14
B_A4
QE4
(TO MCU)
13
B_A3
SII161
QE3
12
B_A2
QE2
11
B_A1
SCDT: high, DE active
QE1
10
B_A0
QE0
9
SCDT
PDO
8
low, staggered O/P
SCDT
7
STAG_OUT
6
VCC
5
GND
4
2516
PIXS
3
470P/0805
ST
2
PD
1
3505
0R/PM5/0805
3506
DFO
1, HIGH O/P DRIVE STRENGTH
3507
10K/PM5/0805
3508
DFO= low, ODCK runs continuously
0, normal ODCK, use falling edge to latch data
3509
0R/PM5/0805
3510
reserved pin, tied high for normal operation
5502
PLL 3V3
BLM31P500S
2517
10U/1206
5503
1
2
ANALOG 3V3
BLM31P500S
3512
10K/PM5/0805
2519
/SI_PDN
10U/1206
(3.3V)
1
2514
7502
10N/0805
MMUN2211
(SI_HS--> to PLD for Hsync filtering)
SI_HS
SI_VS & SI_HS, for MODE DETECTION
SI_VS
SI_VS & SI_DE, to SAA6721
SI_DE
SI_ODCK
3515
47R/PM5/ARV241
R_A0
4
5
RIN_A0
R_A1
3
6
RIN_A1
R_A2
2
7
RIN_A2
R_A3
1
8
RIN_A3
R_A4
4
5
RIN_A4
R_A5
3
6
RIN_A5
R_A6
2
7
RIN_A6
R_A7
1
8
RIN_A7
RIN_A[0..7]
3516
47R/PM5/ARV241
3517
47R/PM5/ARV241
R_B0
4
5
RIN_B0
R_B1
3
6
RIN_B1
R_B2
2
7
RIN_B2
R_B3
1
8
RIN_B3
R_B4
4
5
RIN_B4
R_B5
3
6
RIN_B5
R_B6
2
7
RIN_B6
R_B7
1
8
RIN_B7
RIN_B[0..7]
3518
47R/PM5/ARV241
3519
47R/PM5/ARV241
G_A0
4
5
GIN_A0
G_A1
3
6
GIN_A1
G_A2
2
7
GIN_A2
G_A3
1
8
GIN_A3
G_A4
4
5
GIN_A4
G_A5
3
6
GIN_A5
G_A6
2
7
GIN_A6
G_A7
1
8
GIN_A7
GIN_A[0..7]
3520
47R/PM5/ARV241
3521
47R/PM5/ARV241
G_B0
4
5
GIN_B0
G_B1
3
6
GIN_B1
G_B2
2
7
GIN_B2
G_B3
1
8
GIN_B3
G_B4
4
5
GIN_B4
G_B5
3
6
GIN_B5
G_B6
2
7
GIN_B6
Digital Low
G_B7
1
8
GIN_B7
SCDT
Analog High
GIN_B[0..7]
3522
47R/PM5/ARV241
3523
47R/PM5/ARV241
B_A0
4
5
BIN_A0
B_A1
3
6
BIN_A1
B_A2
2
7
BIN_A2
B_A3
1
8
BIN_A3
10K/PM5/0805
B_A4
4
5
BIN_A4
B_A5
3
6
BIN_A5
B_A6
2
7
BIN_A6
B_A7
1
8
BIN_A7
BIN_A[0..7]
3524
47R/PM5/ARV241
0R/PM5/0805
3525
47R/PM5/ARV241
B_B0
4
5
BIN_B0
B_B1
3
6
BIN_B1
B_B2
2
7
BIN_B2
B_B3
1
8
BIN_B3
10K/PM5/0805
B_B4
4
5
BIN_B4
B_B5
3
6
BIN_B5
B_B6
2
7
BIN_B6
B_B7
1
8
BIN_B7
+3.3V
BIN_B[0..7]
3526
47R/PM5/ARV241
+3.3V
Main panel C.B.A.
Main panel C.B.A.
Component position
Main panel C.B.A.
Back side
180P LCD
53
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