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EN 76
9.
LC7.1E LB
9.5
Video Processing
The video processing is completely handled by the Trident SVP
CX32 video processor which features:
•
CVBS-input for analogue signals.
•
RGB-input for digital (DVB-T) signals.
•
Motion and "edge-adaptive" de-interlacing.
•
Integrated ADC.
•
Built-in 8-bit LVDS transmitter.
•
Colour stretch.
•
Skin colour enhancement.
•
3D Digital Comb Video Decoder.
•
Interlaced and Progressive Scan refresh.
•
TeleText decoding.
•
OSD and VBI/Closed Caption.
9.5.1
Video Application
A n a lo g u e
C V B S _ R F
F ro n t E n d
S C 1 _ R _ IN
S C 1 _ G _ IN
S C 1 _ B _ IN
S C A R T 1
S C 1 _ C V B S _ IN
S C 1 _ F B L _ IN
S C 2 _ Y _ C V B S _ IN
S C A R T 2
S C 2 _ C _ IN
F R O N T _ Y _ C V B S _ IN _ T
S ID E A V
F R O N T _ C _ IN _ T
O n b o a rd E X T 3
H D _ Y _ IN
H D _ P B _ IN
E X T 4
H D _ P R _ IN
IB O _ R _ IN
D i g
F r o n t E n d
IB O _ G _ IN
( D V B-T
IB O _ B _ IN
d e m o d u la to r
IB O _ C V B S _ IN
a n d d e c o d e r)
H D M I_ Y (0 :7 )
H D M I_ C b (0 :7 )
H D M I2
H D M I_ C r (0 :7 )
H D M I
D e c o d e r
H D M I1
Figure 9-5 Block diagram video processing
"Block diagram video processing" shows the input and output
signals to and from the Trident Video Processor in EU
applications.
During analogue reception, a CVBS signal coming from the
analogue front-end is fed to the video processor via pin
CVBS1. During digital reception, the video signal coming from
the MPEG decoder (MOJO) is fed to the video processor via
pins FS1, PC_B, PC_G and PC_R.
The video processor also interfaces the SCART1 & 2 input,
side AV, EXT4 (HD where applicable) and HDMI1 & 2 input.
Through the SCART1 & 2 connectors, a monitor output is
foreseen.
9.5.2
Additional LVDS Interface Panel
An additional LVDS Interface Panel acts as interface between
the SSB and the LCD panel. This is a buy-in panel and
therefore a black-box for Service.
9.6
Memory addressing
Figure "Memory block diagram" shows the interconnection
between the microprocessor, the FLASH memory, the Trident
Video Processor and the SDRAM.
Circuit Descriptions, Abbreviation List, and IC Data Sheets
C V B S 1
P R _ R 2
Y _ G 2
P B _ B 2
P B _ B 3
F B 1
C V B S
C V B S _ O U T 1
SCART 1 Mon. out
P R _ R 3
F S 2
Y _ G 3
C
T r id e n t
Video Processor
SVP CX32
Y _ G 1
P B _ B 1
C V B S
C V B S _ O U T 2
SCART 2 Mon. out
P R _ R 1
P C _ R
P C _ G
P C _ B
F S 1
G_16860_060.eps
150307
7311
CPU_RST/WR/RD/CE
Reneas
A[0:19]
micro-
processor
D[0:7]
CS/WR/RD
7202
A[0:7]
D[0:7]
CX_BA0/BA1/MCLK/
CLKE/CS0/RAS/CAS/WE
Trident CX
CX_BA0/BA1/MCLK/
CLKE/CS0/RAS/CAS/WE
Figure 9-6 Memory block diagram
Control signals CPU_RST, WR, RD and CE, address lines
A[0:19] and data lines D[0:7] are used for transferring data
between the microprocessor (item 7311) and the flash memory
(item 7310). Control signals CS, WR and RD, address lines
A[0:7] and data lines D[0:7] are used for transferring data
between the Trident Video Processor (item 7202) and the
microprocessor (item 7311). Control signals CX_BA0,
CX_BA1, CX_MCLK, CX_CLKE, CX_CS0, CX_RAS, CX_CAS
and CX_WE, address lines CX_MA[0:11] and data lines
DQ[0:15] are used for transferring data between the Trident
Video Processor and the SDRAM ICs (items 7204 and 7205).
7310
1MB
Flash Memory
7204
CX_MA[0:11]
8MB
SDRAM
DQ[0:15]
7205
CX_MA[0:11]
8MB
SDRAM
DQ[16:31]
G_16860_062
220207
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