Lcd Interface Panel - Philips LC7.1E Service Manual

Circuit Diagrams and PWB Layouts

LCD Interface Panel

5
TTL/LVDS PANEL
TT
D
VDISP
J1 J1
0-1453230-3 0-1453230-3
TXAn
1
I14 I14
2
3 TXAp
4
TXBn
5
6
7 TXBp
8 IC2 IC2
THC63LVD824 THC63LVD824
9
10
11 TXCn
GND 76
LVDS_GND1
12
77
RA1-
13 TXCp
78
RA1+
14
79
RB1-
15
80
RB1+
16
LVDD_R 81
LVDS_VCC1
17 TXCLKn
82
RC1-
18
83
RC1+
TXCLKp
19
84
RCLK1-
20
85
RCLK1+
21
86
C RD1-
22
87
RD1+
23 TXDn
88
GND LVDS_GND2
24
89
RA2-
TXDp
25
90
RA2+
26
R52 R52 not used 91
RB2-
27
0R 0R 92
RB2+
28
3V3_1G
I13 I13 93
LVDD_R LVDS_VCC2
29
94
RC2-
IC3 IC3
30 5
74LVC1G125 74LVC1G125 not used 95
RC2+
32 31 1
OEn OEn
GND
4 96
Y Y RCLK2-
2
A A
97
RCLK2+
3
98
RD2-
GND GND 99
RD2+
3V3_1G
100
GND
LVDS_GND3
R47 R47
BC858W BC858W
not used
T2 T2
10K 10K R44 R44
T1 T1
OE_823
BC848W BC848W
1K 1K
for 2 x LVDS only
R45 R45
PDWNn_823
1K 1K
R46 R46
1K 1K
GND GND GND GND GND
B
3V3_1G LVDD_R PVDD_R VDD3_R LVDD_T PVDD_T VDD3_T
+3V3
J2 J2
L17 L17
1
BLM18EG221SN1D BLM18EG221SN1D
2
3 I15 I15 L11 L11 I16 I16
4
BLM18EG221SN1D BLM18EG221SN1D
5
L12 L12 I17 I17
7 6
GND BLM18EG221SN1D BLM18EG221SN1D
B5B-PH-SM3-TB B5B-PH-SM3-TB
L13 L13 I18 I18
BLM18EG221SN1D BLM18EG221SN1D
L14 L14 I19 I19
BLM18EG221SN1D BLM18EG221SN1D
L15 L15 I20 I20
BLM18EG221SN1D BLM18EG221SN1D
L16 L16 I21 I21
BLM18EG221SN1D BLM18EG221SN1D
for 2 x LVDS only
+ +
C19 C19
C26 C26 C20 C20 C21 C21 C22 C22 C23 C23 C24 C24
100uF 100uF
100nF 100nF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF
16V 16V
GND GND GND GND GND GND GND GND
for 2 x LVDS only
A
PHPCB0002800
5
LC7.1E LB
4
to LCD / TTL-CMOS
J4 J4
0-1453230-4 0-1453230-4
GND
VDD3_R VDD3_R
GND GND
50
R15
49 GND
GND7
48
VCC5 VDD3_R
47
R14
46
R13
LVDS RECEIVER 45
R12
44
R11
43
R10
THC63LVD824
42
GND6 GND
41
VDD3_R
VCC4
40
CLKOUT
39
B27
38
B26
37
B25
36
B24
35
B23
34 GND
GND5
33
VCC3 VDD3_R
32
B22
31
B21
30
B20
29
G27
28
GND4 GND
27
VCC2 VDD3_R
26
G26
GND GND GND GND
VDD3_R
PVDD_R
+3V3
1K 1K R12 R12
1K 1K R27 R27
1K 1K R28 R28
1K 1K R29 R29
1K 1K R30 R30
C25 C25
4.7uF 4.7uF see THC63LVD824
configuration table below
GND
LVDD_R PVDD_R
GND GND
THC63LVD824 configuration Table
20 Inch (TTL/CMOS) 19 Inch (2 x LVDS)/ Test
L H L H
PDWNn R14 X R12 Normal operation R14 X R12 Normal operation
MODE 0 X R15 R27 Dual link R15 X R27 Single link
MODE 1 X R16 R28 always L X R16 R28 always L
R/F X R17 R29 Falling edge X R17 R29 Falling edge
DVRSEL Low power Low power
X R18 R30 X R18 R30
4
7. 66
3
42
44
43
41
VDISP
GND GND GND GND GND GND GND GND
C18 C18
47pF 47pF
GND
VDD3_T
GND
IC1 IC1
THC63LVD823A THC63LVD823A
B15 76
47R 47R R7B R7B B15
R15
B16 77
B16
B17 78
B17
R20
47R 47R R7A R7A 79
R20
R14
R21
R6D R6D 80
47R 47R R21
R13
R22 81
47R 47R R6C R6C R22
R12
R23 82
47R 47R R6B R6B R23
R11
R24 83
47R 47R R6A R6A
R24
R10
R25
84
R25
R26
85
R26
R27 86
R27
87
47R 47R R38D R38D VDD3_T VCC4
B27
88
47R 47R R38C R38C GND
GND5
B26
G20
47R 47R R38B R38B 89
G20
B25
G21
R38A R38A 90
47R 47R G21
B24
G22 91
47R 47R R39D R39D G22
B23
G23 92
G23
G24 93
G24
G25
47R 47R R39C R39C 94
G25
B22
G26
R39B R39B 95
47R 47R G26
B21
G27 96
47R 47R R39A R39A G27
B20
B20 97
47R 47R R40D R40D B20
G27
B21 98
B21
B22
99
B22
B23
R40C R40C 100
47R 47R B23
G26
SHCLK
47R 47R R40B R40B
G25
47R 47R R40A R40A
G24
47R 47R R41D R41D
G23
47R 47R R41C R41C
G22
GND
47R 47R R41B R41B
G21
VDD3_T
47R 47R R41A R41A
G20
47R 47R R42D R42D
R27
47R 47R R42C R42C
R26
47R 47R R42B R42B
R25
47R 47R R42A R42A
R24
47R 47R R43D R43D
R23
47R 47R R43C R43C
R22
47R 47R R43B R43B
R21
47R 47R R43A R43A
R20
for 2 x LVDS only
VDD3_R LVDD_T
GND GND
THC63LVD823A configuration Table
Test
L H
PDWNn R25 X R31 Normal operation
MODE 0 R23 X R33 Single out
MODE 1 X R22 R34 Dual in
R/F X R19 R37 Falling edge
RS Normal swing output
R20 X R36
O/E R24 X R32 Output enabled
PRBS X R26 R13 PRBS Disable
MAP R21 X R35 Map Mode 1
3
2
VDD3_T
GND
50
LGND3 GND
49
TA1-
48
TA1+
47
TB1-
46
TB1+
45
LVCC2 LVDD_T
LVDS TRANSMITTER
44
TC1-
43
TC1+
THC63LVD823A 42
TCLK1-
41
TCLK1+
40
TD1-
39
TD1+
38
GND
LGND2
37
TA2-
36
TA2+
35
TB2-
34
TB2+
33
LVDD_T
LVCC1
32
TC2-
31
TC2+
30
TCLK2-
29
TCLK2+
28
TD2-
27
TD2+
26 GND
LGND1
GND GND GND GND
PVDD_T
VDD3_T
1K 1K R13 R13
1K 1K R31 R31
1K 1K R32 R32
1K 1K R33 R33
1K 1K R34 R34
1K 1K R35 R35
1K 1K R36 R36
1K 1K R37 R37
see THC63LVD823A
GND
configuration table below
PVDD_T VDD3_T
for 2 x LVDS only
GND GND
19 Inch (2 x LVDS)
L H
R25 X R31 Normal operation
X R23 R33 Dual out
X R22 R34 Dual in
X R19 R37 Falling edge
Normal swing output
R20 X R36
R24 X R32 Output enabled
X R26 R13 PRBS Disable
X R21 R35 Map Mode 2
2
1
TT
D
L1 L1
DLW21SN670SQ2 DLW21SN670SQ2
J3 J3
L2 L2 0-1453230-3 0-1453230-3
RXO0n 1
DLW21SN670SQ2 DLW21SN670SQ2 RXO0p 2
RXO1n
3
L3 L3
RXO1p
4
DLW21SN670SQ2 DLW21SN670SQ2 RXO2n 5
RXO2p 6
L4 L4
7
RXOCn
DLW21SN670SQ2 DLW21SN670SQ2 8
RXOCp
9
L5 L5
RXO3n 10
C
RXO3p 11
DLW21SN670SQ2 DLW21SN670SQ2
RXE0n 12
L6 L6 RXE0p
13
14
DLW21SN670SQ2 DLW21SN670SQ2
RXE1n 15
L7 L7
RXE1p 16
17
DLW21SN670SQ2 DLW21SN670SQ2
RXE2n
18
L8 L8 RXE2p
19
RXECn 20
DLW21SN670SQ2 DLW21SN670SQ2
RXECp 21
L9 L9
RXE3n 22
RXE3p
23
DLW21SN670SQ2 DLW21SN670SQ2 I43 I43
24
L10 L10
25
26
DLW21SN670SQ2 DLW21SN670SQ2
27
I42 I42
28
29
30
31 32
GND
VDISP
B
A
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