Table of Contents
Advertisement
IC
TC74VHC125FS(EL) (TOSHIBA)
C-MOS BUS BUFFER GATES WITH 3-STATE OUTPUT
-TOP VIEW-
14
13
12
11
10
9
V
DD
1
2
3
4
5
6
NOTE :
TYPE
V
DD
74AC/
+2 to +5.5V
74VHC
74ACT/74HCT
+4.5 to +5.5V
74LCX
+2 to +3.6V
74LVT/74LVC
+2.7 to +3.6V
OTHER TYPES
+2 to +6V
TC74VHC14FS(EL) (TOSHIBA)FLAT PACKAGE(SMALL)
C-MOS HEX SCHMITT TRIGGER INVERTERS
—TOP VIEW—
14
13
12
11
10
9
V
DD
1
2
3
4
5
6
NOTE :
TYPE
V
DD
TC74AC/VHC
+2V to +5.5V
OTHER TYPES
+2V to +6V
TC74VHC157FS(EL) (TOSHIBA)
C-MOS QUAD 2-LINE-TO-1-LINE DATA SELECTOR/ DEMULTIPLEXER
—TOP VIEW—
INH
Y0
Y1
YC
X0
IN
IN
IN
OUT
IN
16
15
14
13
12
11
V
DD
1
0
0
0
1
1
1
2
3
4
5
6
A
V0
V1
VC
W0
W1
IN
IN
IN
OUT
IN
IN
NOTE:
V
TYPE
DD
74ACT/74FCT
+5V
TC74AC157P
+2 to +5.5V
TC74AC157
TC40H
+2 to +8V
OTHER TYPES
+2 to +6V
14-36
G
8
A
Y
G
A
Y
0
0
0
0
1
1
1
X
HI-Z
GND
0
; LOW LEVEL
7
1
; HIGH LEVEL
X
; DON'T CARE
HI-Z
; HIGH IMPEDANCE
Y = A
A
Y
8
V
IN
Y = A
V
OUT
V
2.0V
A
Y
4.5V
0
1
6.0V
1
0
GND
0
;
LOW LEVEL
7
1
;
HIGH LEVEL
V
V
N
P
X1
XC
2
V0
IN
OUT
3
V1
VC
10
9
5
W0
1
6
W1
WC
0
11
X0
10
X1
XC
GND
7
8
WC
Y0
14
OUT
13
Y1
YC
A
INH
1
15
CONT.IN
ON
CHANNEL
INH
A
0
0
0
0 ; LOW LEVEL
0
1
1
1 ; HIGH LEVEL
1
X
GND
X ; DON'T CARE
TC74VHC164F (TOSHIBA)FLAT PACKAGE
TC74VHC164FS(EL)
C-MOS 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER
—TOP VIEW—
A
1
B
2
Q1
3
Q2
4
Q3
5
Q4
6
7
GND
NOTE:
TYPE
AC/VHC
HC
HCT
Q1
3
8
CK
1
A
2
D
Q
B
R
D
9
RD
V
OUT
V
V
DD
N
P
0.75V
1.25V
1.9V
2.7V
2.6V
3.6V
V
IN
TC74VHC574FS(EL) (TOSHIBA)FLAT PACKAGE(SMALL)
C-MOS 3-STATE D-TYPE EDGE-TRIGGERED FLIP-FLOP
-TOP VIEW-
EN
1
IN
D1
2
IN
D2
3
IN
D3
4
IN
D4
5
IN
D5
6
IN
D6
7
IN
D7
8
IN
D8
9
4
IN
10
GND
7
D1
2
9
12
11
CK
1
EN
NOTE;
TYPE
74HC
74AC/74VHC
74ACT/74FCT/74HCT
74LCX
74LVC
3
Q1
V
DD
14
4
Q2
1
5
A
Q3
13
Q8
D
6
2
B
Q4
10
Q5
12
Q7
11
8
Q6
12
Q7
11
Q6
13
Q8
R
D
10
Q5
9
9
R
D
INPUTS
OUTPUTS
R
CK
A
B
Q1
Q2
D
8
CK
0
X
X
X
0
0
0
1
0
X
X
Q1o
Q2o
1
1
1
1
Q1n
1
0
X
0
Q1n
1
X
0
0
Q1n
V
DD
+2 to +5.5 V
+2 to +6 V
+5 V
Q2
Q3
Q4
Q5
4
5
6
10
D
Q
D
Q
D
Q
D
Q
D
Q
R
R
R
R
R
D
D
D
D
D
2
19
D1
Q1
V
20
DD
3
18
D2
Q2
4
17
D3
Q3
19
Q1
OUT
5
16
D4
Q4
6
15
D5
Q5
18
Q2
OUT
7
14
D6
Q6
8
13
D7
Q7
17
Q3
OUT
9
12
D8
Q8
11
16
Q4
OUT
EN
1
15
Q5
OUT
14
Q6
OUT
13
Q7
OUT
12
Q8
OUT
11
CK
IN
Q1 D2
Q2 D3
Q3 D4
Q4 D5
Q5 D6
Q6 D7
19
3 18
4 17
5 16
6 15
7 14
D Q
Q
EN
V
DD
+2 to +6V
+2 to +5.5V
+4.5 to +5.5V
+2 to 3.6V
+2.7 to 3.6V
Q8
0
Q8o
Q7n
0
;
LOW LEVEL
Q7n
1
;
HIGH LEVEL
Q7n
X
;
DON'T CARE
Q6
Q7
Q8
11
12
13
D
Q
D
Q
R
R
D
D
EACH FLIP-FLOP
INPUTS
OUT
EN
CK
D
Q
0
1
1
0
0
0
0
X
Q
0
1
X
X
HI-Z
0
; LOW LEVEL
1
; HIGH LEVEL
X
; DON'T CARE
HI-Z
; HIGH IMPEDANCE
Q
; NO CHANGE
0
Q7 D8
Q8
8 13
9
12
D
Q
Q
EN
DSR-1/1P/V2
Advertisement
Table of Contents
